SU222012A1 - PROGRAMMING AND STORAGE DEVICE - Google Patents

Description

Known memory devices containing triggers.

The proposed device is characterized in that it comprises a group of valves connected in series, the control input of each of which is connected to the corresponding memory trigger, and a second group of valves, the control input of each of which is connected to the output of the previous trigger, and the signal inputs are connected to the outputs of the corresponding valves of the first group, the outputs of the valves of the second group are connected to the outputs of the corresponding triggers, each control input of the valves of the third group is connected to the second ; the device's input rum, the signal input of each valve of the third group is connected to the output of the next trigger, and the output to another input of the corresponding trigger.

This makes it possible to reduce the number of devices in the device.

On f, ig. 1 is a block diagram of the proposed programming and storage device; in fig. 2-variant of the circuit with trigger on semiconductor triodes and electronic keys on semiconductor diodes.

keys B connected in series and C keys branched from them, through which the pulses from the clock generator D are sent to 1 trigger inputs, and keys A,

voltage controlled by the & balance indicator.

Before starting, all the triggers are triggered to their original position by the reset circuit (shown in Fig. "E shown). In this state, the left lures of the triggers are closed, and the right ones are open. In this case, the keys are open, and the keys are closed.

Transmission pulse from the clock generator D through the keys B ,, + i, В „,. . ., Bj arrive at

trigger input T and overturns it. The TI trigger closes the BI key, which prevents the second impulse from the clock generator from being driven to the trigger input TI, and closes the € -2 key, allowing it to

pulse to trigger trigger g.

The second imiuls from the clock generator through the keys, В „, ..., V., and € - goes to the input of the trigger T. and overturns it. The Gz trigger closes the Vu key, which prevents the third pulse from passing through the clock generator to the input of the Go trigger, and opens the Cz key, which allows the passage of this pulse to the Gz trigger input.

Laisa to the key A receives the opening voltage, then the pulse from the trigger T passes to the input of the trigger TI and | B103 Rotates it to its original state, B 1 Protect; in the first case, the trigger TI remains on.

Returning the trigger TI to the initial state 1and changing the state of keys A and BI does not affect the sequence of operation of the rest of the circuit.

Similarly, when the third and next pulses arrive, the rest of the circuit works.

The rt-th pulse from the clock generator through the keys 5 „+1, В„ and С „goes to the trigger input T„ and overturns it. Trigger G „closes the key B„ and opens the key С n-ri, after which the next impulse can pass to the trigger Tn + i

() - the imiuls from that | whoever generator through the keys B «+ i and C„ +1 enters the trigger input and the OP | turns it. The trigger Тп + 1 closes the Bn + i keys, turns off the entire circuit from the clock generator in such a way, and subsequent pulses do not change the state of the circuit.

Simultaneously with the trigger Tn + i, an impulse is sent to the key L. This “multiplier, in the presence of an enabling voltage from the balance indicator f, returns the trigger T” to the initial state. In the absence of an enabler, the trigger G remains on.

At STOiM, the duty cycle is terminated, the circuit arrives in the ready state. Next cycle.

For proper operation of the device, it is necessary that the moment of overturning of the memory trigger is slightly ahead of the moment when the corresponding voltage appears from the balance indicator E. Then, when a pulse is given from any trigger to key A of the previous one, the latter will be opened or closed according to the voltage coming from balance indicator B.

In the circuit shown in FIG. 2, the pulses 5 from the clock generator and the pulses followed by the trigger to the previous one have a positive polarity. In the initial state, the voltage on the left shoulder of the trigger is negative and approximately equal to the voltage of the power source, and on the right side - approximately zero. The resolving voltage from the balance indicator f is zero, and the inhibiting voltage is to some negative voltage.

5 The proposed device can be applied to digital and cyclic transducers operating on the principle of weighing the measured value.

Subject invention

A programming and storage device containing triggers, characterized in that, in order to reduce the number of equipments, iOHO contains a group of series-connected gates, the control input of each of which is connected to the corresponding memory trigger, and the second rpyniny Gate, which controls each input which are connected to the output of the previous trigger, and the signal inputs are connected to the outputs of the corresponding valves of the first group, the outputs of the valves of the second group are connected to the outputs

5 corresponding triggers, each control input of valves of the third group is connected to the second input of the device, the signal input of each valve of the third group is connected to the output of the next trigger,

and the output is with another input of the corresponding trigger.