SU1753622A1 - Secam decoder color synchronizer - Google Patents

Abstract

The invention relates to television technology and can be used in television receivers of the SECAM system. The purpose of the invention is to improve noise immunity. The color synchronization device of the SECAM decoder contains the averager 1, the selector 2 of the SECAM signal, the D-flip-flop 3, the AND 4 element, the accumulation unit 5, the switch control unit 6, the chromaticity switch 7, the pulse shaper 8. The SECAM signal selector 2 is designed as a comparator 9-1, 9-2 and RS-rsgger 10, accumulation block 5 is in the form of a counter 11 and a decoder 12, switch control block 6 is a counting trigger 13, element EXCLUSIVE OR 14 and D- trigger 15, switch 7 chromaticity - RS-trigger 16 and D-flip-flop 17, and shaper 8 pulses - counting trigger 18, elements U 19-1, 19-2 and D-flip-flop 20. 2 з, п.ф-л, 3 il.

Description

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The invention relates to television technology and can be used in television receivers and video monitoring devices of the SECAM system.

The purpose of the invention is to improve noise immunity.

Figure 1 shows the electrical block diagram of the color lock device of the SECAM decoder; 2 and 3 are timing diagrams explaining its operation.

The color synchronization device of the SECAM decoder contains an averager 1, a SECAM signal selector 2, a D-flip-flop C, an AND 4 element, an accumulation block 5, a switch control block b, a chroma switch 7, a driver 8 pulses, where the SECAM first selector 2 1 and the second 9-2 comparators and the RS flip-flop 10, the accumulation unit 5 in the form of a counter 11 and a decoder 12, the switch control unit 6 in the form of a counting flip-flop 13, the EXCLUSIVE OR 14 element and the D-flip-flop 15, the chromaticity switch 7 - in the form of RS flip-flop 16 and D flip-flop 17, and the former l 8 pulses in the form of a counting trigger 18, elements And 19-1, 19-2 and D-flip-flop 20.

The color synchronization device decoder SECAM works as follows.

The input of the averager 1 receives a digital color difference signal from the output of the frequency detector of the digital decoder SECAM, which is not shown in Fig. 1. Averager 1 is unlocked by gating pulses (Fig. 2a), which coincide in time with the rear platforms of striking extinguishing pulses. As a result, digital signals are output at the output of the averager 1, corresponding to the averaged demodulated color subcarrier packets. If the frequency detector is tuned to the frequency lying in the middle between the quiescent frequencies for and 0 in the chrominance signals, then the signal at the output of the averager

1 will be in the form of groups of samples U1 of a different sign, conventionally shown in fig.2b. The values of the samples in each group are the same and correspond to the levels of the black dr, de areas in the R-Y and B-Y lines. These signals arrive at the first inputs of the first 9-1 and second 9-2 comparators in the selector.

2SIGNAL SECAM. At their second inputs, binary constants Е1 and Е2 are applied, which correspond to the given values of the sites dr, de. The first 9-1 and second 9-2 comparators are triggered if the signal falls into the D zones determined by the input signal E1 and E2 constants. At the same time,

their outputs are separated by single-bit pulses at the inputs of RS-flip-flop 10. If the SECAM program is received, the dr, ds signals alternate in time, causing the RS-flip-flop 10 to trigger, and a half-line voltage voltage regulator shown in FIG. 2c. When PAL or NTSC programs are accepted in which the flash frequencies are the same in all rows, the polarities of the U1 signal samples will be the same, for example, positive. Even if the amplitudes of these samples coincide with the value of one of the constants, for example, E1 (which is not very high),

5, the RS flip-flop 10 switches to one of its operating states and at its output, instead of the half-line frequency meander, a logical zero or logical unit will be maintained.

0 The signal from the output of the selector 2 of the SECAM signal passes to the information input of the D-flip-flop Z. When the SECAM program is received, this signal takes the form of a half-line frequency meander (Fig. 2b). On

5, the counting input of the D-flip-flop 3 receives the building pulses (Fig. 2a). D-flip-flop 3 triggers on the falling edge of these pulses. At its output Q, a voltage square wave is shown, shown in Fig. 2d.

0 Element And 4 forms from signals (figv, g) pulses (figd) of the semi-line frequency, which are present, for example, in the dr lines, i.e. tightly coupled to the phase switching signals in the encoder.

5When receiving PAL, NTSC or

A black and white program at the output of the selector 2 maintains a signal with a logic zero or logic unit level. Then, at the output of the D-flip-flop H, a unit or zero is set, respectively. In both cases, the output of the And 4 element will be a signal with a logic zero level. Thus, the pulses at the output of the element And 4 appear only when receiving the signal SECAM.

5 These pulses trigger the counter 11. At the last counting cycle, a signal appears at the output of its most significant bit, which, in combination with the pulse from AND 4, triggers the decoder 12, to

The output of which appears is a pulse (Fig. 3b), shifted in time with respect to the counter reset pulse (Fig. 3a) by the accumulation time g. The impulse from the accumulation unit 5 goes to the control unit b.

5 switch and the input switch 7 color. In block 6, a pulse from accumulation block 5 passes to the counting input of D-flip-flop 15, to the input D of which a half-line frequency meander is fed from the counting flip-flop 13. If the phase of the counting flip-flop 13

coincides with the phase of the switching signal in the encoder, then the pulse from the decoder 12 corresponds in time to a logical zero at the output of the counting trigger 13. The output of the D-trigger 15 sets a logical zero and the EXCLUSIVE OR 14 element will pass the signal from the counting trigger 13, not inverting it, If the phase of the counting flip-flop 13 is not activated at the output of the D-flip-flop 15, a logical unit is established and the EXCLUSIVE OR 14 element inverts the signal. Therefore, at the output of block 6, the meander phase of the voltage of the half-line frequency corresponding to the switching phase in the encoder is maintained. This ensures the correct phase switching signals in the decoder.

When a pulse appears at the output of the decoder 12, the RS-flip-flop 16 in the chroma switch 7 is switched to the state when a logical unit appears at its output (Fig. 3g). With the arrival of the polling pulse (FIG. 3b), the D-flip-flop 17 forms a logical unit at its output, which ensures the inclusion of a color channel (FIG. 3). The reset and interrogation pulses (Fig. 3b, b) necessary for the operation of the device can be produced by the pulse shaper 8.

The shaper contains a counting trigger 18 driven by field pulses, and a D-trigger 20, on the synchronous input of which gates lower-case pulses arrive, and the input D is field quenching pulses. The output signals 6 and Q of the counting flip-flop 18 and D-flip-flop 20 are compared in AND 19-1,19-2 elements, which produce pulses with a frame repetition frequency shifted by one field. These pulses serve as reset and interrogation signals (fig.Za, b).

As a result, the SECAM signal selector 2 generates a pulse at the output only if the polarity of the input signal U1 alternates in rows and its levels are close to the values of the constants E1 and E2. Such conditions are satisfied only when the SECAM signal is received.

Claims (3)

Claim 1. SECAM color decoder color synchronization device containing an accumulation unit made in the form of serially connected pulse counter, whose information input is the information input of the accumulation unit and the decoder, the output of which is the output of the accumulation unit, as well as the control unit of the electronic switch, synchronous input which is the entrance horizontal sync pulses, characterized in that, in order to improve noise immunity, a serially connected averager is inputted, the input of which is the information input of the color synchronization device of the SECAM decoder of the SECAM signal selector, the D input element and the second input of which is connected to the output of the CE10 signal selector QAM, and the output is connected to the information input of the accumulation, the output of which is connected to the information input of the control unit by the electronic switch, the output of which is the output of semi15 line The second color clock of the SECAM decoder, the pulse shaper, the first and second inputs of which are respectively the frame sync input and the first input of the strobe pulses of the color synchronization device of the SECAM decoder, and the color switch, the first input of which is connected to the first output of the pulse puller, the second input is connected to the installation input of the accumulation unit and the second output of the pulse former, the third input is connected to the output of the accumulation unit, and the output is control l yuschim output device color sin0 hronieatsii SECAM decoder. the clock input of the averager is the clock input of the color synchronization device of the SECAM decoder, the second gate input of which is the averaging input of the averager and the C input of the D-flip-flop. 2. Pop 1 device, characterized in that the SECAM signal selector is designed as an RS flip-flop, as well as the first and 0 of the second comparators, the first inputs of which are combined and are the input of the signal selector SECAM, the second inputs are the inputs of constant signals, and the outputs are connected respectively to S- and 5 R-inputs RS-flip-flop, the output of which is the output of the signal selector SECAM. 3. Pop 1 device, characterized in that the control unit of the electronic switch is designed as a counting 0 of the flip-flop, the input of which is the synchronous stroke of the control unit of the electronic switch, the D-flip-flop, the C input of which is the information input of the control unit of the electronic switch, and 5 is also an EXCLUSIVE OR element, the first input of which is connected to the D input of the D-flip-flop and the output of the counting trigger, the second input is connected to the output of the D-flip-flop, and the output is the output of the control unit of the electronic switch. № /