SU1744563A1 - Vehicle technical state diagnosing stand - Google Patents

Abstract

This invention relates to a transport engineering and can be used in assessing the technical condition of a vehicle. The purpose of the invention is to improve the accuracy of diagnosis of the vehicle. The bench contains support rollers 2, a roller rotation frequency sensor 5, an adjustable hormone kinematically connected to the rollers, an adjustable brake torque sensor 6, an automatic control system 12, a logic unit 15, and a computing device 16. 5 Cpf. 2 Il. J.i

Description

This invention relates to a transport engineering industry and can be used in assessing the technical condition of an engine and transmission of a vehicle.

A well-known stand is used to determine the maximum power at the wheels in the mode of stabilization of speed and the power of losses in the transmission during coasting, while the engine power is equal to the sum of these powers.

The disadvantage of this test bench is the low accuracy of measurement of transmission loss power due to the low accuracy of determining the moment of inertia of rotating masses.

A stand is known that allows determining with sufficient accuracy the total power loss in the transmission and stand in the coasting mode in two stages.

The disadvantage of this stand is the difficulty of determining the power of the engine, which means that it is necessary to first determine the maximum tractive power on the wheels in the mode of stabilization of speed, then the losses in the transmission and in the stand, and then these values are summed up.

The closest to the proposed technical entity is a stand that allows with sufficient accuracy to determine the engine power and losses in the transmission and stand in three stages: two stages of acceleration and a run-down stage, containing support rollers, an adjustable brake, kinematically connected to the support rollers , a speed sensor of the support rollers with a normalizing converter, a torque sensor of an adjustable brake with a normalizing converter, a recording device and a differentiator, a setting block, three a comparator, a signaling device, an automatic control system, where a switch is installed between the error amplifier and the power element control unit; a logic unit; a computing device registering a power device; the logic unit contains an inverter, three elements 2 AND, two elements 2 AND-NOT, a resistor and the Reset button.

The Reset button resets the previous measured value of the engine power and the circuit is reset.

Vehicle acceleration begins with a constant load M0. The load condition in the transmission is ensured by a closed automatic control system, in which the signal from the setting block is compared with the feedback signal from the output of the normalizing converter.

torsional moment. The difference of the signals is amplified by the error amplifier and through the open switch and the control unit of the power elements enters the control element of the adjustable

brakes.

When the value of the rotation frequency of the first comparator is reached, the values of the additional load M0 and the acceleration rate Јi are fixed in the three memory blocks of the computing device. At the same time, the automatic control switch opens and the control element of the adjustable brake is removed.

the signal, the load created by the brake, is removed. Further acceleration is carried out without additional load M0. At the end of the transient process, the load is removed upon reaching the frequency

rotation triggering of the second comparator in the fourth memory block of the computing device is recorded acceleration value значение2. When the value of the rotation frequency of the third comparator is reached, the signaling device is turned on. The engine is turned off and the vehicle is switched to coast down. At decrease in frequency of rotation - at the moment of release of the first

the comparator in the fifth memory block of the computing device records the value of the deceleration S3.

The computing device, using the values of M0, co, Јi, Ј2 and Јz, calculates the value of the engine power by the formula

N Mo (Ј1 + Ј3)

A disadvantage of the known stand is that the acceleration stage begins with a constant additional load M0. After the load is dumped, at the moment the first comparator is triggered, the transitional process of establishing the value of a new, greater acceleration of acceleration without

load, which takes a certain time, and the longer this time, the lower the accuracy of the power measurement. Moreover, in the measurement process, the readings on the recording devices continuously change, which causes inconvenience in reading information,

The purpose of the invention is to improve the accuracy of diagnosing transport media.

stability, operation and ease of reading information.

The goal is achieved by the fact that, in a stand that contains support rollers mounted on the base, an adjustable brake, kinematically connected to the support rollers, a rotational speed sensor of the support rollers with a normalizing converter, a torque sensor of the adjustable brake with a normalizing converter, a speed recorder, a differentiator, the block of settings, the first, second and third comparators, an automatic control system having an error amplifier, a switch, the first input of which is connected not with the output of the error amplifier, the control unit of the power elements, the input of which is connected to the output of the switch, a signaling device, a logic unit, a computing device registering a power device, while the logic unit contains two elements 2I-NOT, two elements 2Y, a resistor normally open contact, inverter, entered two elements ZI.

In the proposed stand, the logical unit consists of the known elements 2I, ZI.2I-NOT and the inverter, however, in this connection with the other elements of the circuit, it allows the acceleration process to be carried out in two steps in the following sequence. First comes the stage of acceleration without additional load, and then the stage with an additional reference load M0. Changing the order of load in the proposed stand compared to the prototype allows to reduce the time of the transition process to the steady state of the second stage.

Fig. 1 shows a structural scheme. MA of the proposed booth; in fig. 2 is a graph of changes in the speed of rotation of the SU of the driving wheels, the load M on the driving wheels, and the angular acceleration of the driving wheels with time.

The stand contains base 1 mounted on the base and supporting 2 support rollers, an adjustable brake 3, kinematically connected to leading support rollers 1, a sensor 4 of the rotational speed of the support rollers with a normalizing converter 5, a variable brake torque sensor 6 with a normalizing converter 7, the first 8 , second 9 and third 10 comparators, setpoint block 11, automatic control system 12, speed recorder 13, differentiator 14, logic unit

15, the computing device 16. recording the power device 17 and the signaling device 21.

The automatic control system 12 comprises an error amplifier 18, a switch 19 and a power element control unit 20.

Logic unit 15 contains the first element ZI 22, inverter 23. second element ZI 24, first 25 and second 26 elements 2I, RS flip-flop on first 27 and second 28 elements 2I-NO, resistor 29 and normally open contact (button) 30 Reset.

The computing device contains 5 first 31, second 32, third 33, fourth 34 and fifth 35 memory blocks, first adder 36, divider 37, sixth memory block 38, first 39 and second 40 multipliers, first switch 41, second adder 42 , 0 the second 43 and the third 44 switches, the third multiplier 45, the fourth switch 46 and the fifth switch 47.

The setting unit 11 is four resistor voltage dividers and 5 generates voltages corresponding to

ShZ, Sh2- and MoKomparatora 8, 9 and 10 are made on the basis of integrated circuits and have a output signal equal to the logical unit

0 when the rotational speed of the support rollers is lower than the corresponding setpoint.

The signaling device 21 is a controlled multivibrator, at the output of which a light

5 boards Disable the engine.

Switches 19.41, 44.45 and 47 are made on the basis of bi-directional proximity switches in an integral design. Switch 49 is a button with normally closed and normally open contacts.

The memory blocks are made on the sampling-storage circuits, the adders - on the operational amplifiers, the divider and the resident inhabitants - on the basis of the integrated circuit of the analog multiplier,

The output of the normalizing Converter 5 is connected to the input of the differentiator 14, the second inputs of the first 8, second 9 and

0 of the third 10 comparators and the second input of the computing device 16. The output of the differentiator 14 is connected to the first input of the computing device 16. The first input of the first comparator 8 is connected to the third input of the setting unit 11, the first input of the second comparator 9 - to the second output of the setting unit 11, the first the input of the third comparator 10 - with the first output of the block 11 settings. The output of the first comparator 8 is connected to the first input.

logic unit 15, the output of the second comparator 9 with the second input of logic unit 15, the output of the third comparator 10 with the third input of the logic unit 15 and the input of the signaling device 21. The output of the normalizing converter 7 is connected to one of the inputs of the error amplifier 18 and the third input of the computing device 16. The fourth output of the setpoint unit 11 is connected to another input of the error amplifier 18, the output of which is connected to the second input of the switch 19. The control input of the switch 19 is connected to the second output of the log eskogo unit 15, and an output - to an input of the control unit 20 force elements, whose output is connected to the input of the control element reguliruemogotormozaZ. The first to sixth outputs of the logic unit 15 are connected respectively to the fourth to ninth inputs of the computing device 16. The first output of the computing device 16 is connected to the speed recorder 13, and the second to the power recorder 17.

As part of the logic unit 15, its second input is connected to the first input of the first element ZI 22, the output of which is connected to the second output of the logic unit 15. The first input of the logic unit 15 is connected to the input of the inverter 23 and the second inputs of the elements 2I 25 and 26. The output of the inverter 23 is connected with the second inputs of the elements ZI 22 and 24. The third input of the logic unit 15 is connected to the first input of the element 2I-NOT 27 and the first input of the second element ZI 24. The third input of the element ZI 22 is connected to the first input of the first element 2I 25, the second input of the first element 2I -NO 27, out ohom second element 2I-NOT 28 and fifth output of the logic unit 15. The third input of the second element ZI 24 is connected to the first input of the second element 2I 26, the first input of the second element 2I-NOT 28, the output of the first element 2I-NOT 27 and the sixth output logical unit 15. The output of the second element ZI 24 is connected to the third output of the logic unit 15. The output of the first element 2 and 25 is connected to the first output of the logical unit 15. The output of the second element 2 and 26 is connected to the fourth output of the logical unit 15. The second input of the second element 2 AND-NOT 28 through a resistor 29 the positive terminal of the current source. A normally open contact (reset button 30) is connected to the resistor 29 and the negative terminal of the current source.

As part of the computing device 16, the input of the first memory block 31 is connected to the third input of the computing device 16, the input of the second memory block 32 to the second input of the computing device 16, the inputs of the third 33, fourth 34 and fifth 35 memory blocks are combined and connected to the first input of the computing device 16. The control circuits of the second 32 and third 33 memory blocks are connected to the fourth input of the computing device 16. The control circuits of the first 31 and

the fourth 34 memory blocks are connected to the fifth input of the computing device 16. The control circuit of the fifth memory block 35 is connected to the sixth input of the computing device 16. The output of the third

memory 33 is connected to one of the inputs of the first adder 3-6 and the first input of the first multiplier 39. The output of the fourth memory block 34 is connected to another input of the first adder 36. The output of the first memory block 31 is connected to one of the outputs of the divider 37. The output of the first adder 36 is connected to another input of the divider 37, the output of which is connected to the input of the sixth memory block 38, the output of which is connected

the second input of the multiplier 39 and the first input of the second multiplier 40. The control circuit of the sixth memory block 38 is connected to the eighth input of the computing device 16 The output of the fifth memory block is connected to the second input of the second multiplier 40. The output of the first multiplier 39 is connected to the first input of the second adder 42, the second input of which is connected to the output of the first switch

41, the first input of which is connected to the output of the second multiplier 40. The control circuit of the first switch 41 is connected to the seventh input of the computing device. Output of the second adder

connected to the first input of the second switch 43, the output of which is connected to the second input of the multiplier 45 and the output of the third switch 44, the input of which is connected to the output of the first

the switch 41. The control circuit of the second switch 43 is connected to one output of the normally closed contact of the fifth switch 47. The control circuit of the third switch 44 is connected

with one output of the normally open contact of the fifth switch 47. The other outputs of the contacts of which are combined and connected to the positive terminal of the current source. The output of the second memory block 32 is connected to the first input of the third multiplier 45 and the first output of the computing unit 16. The output of the third multiplier 45 is connected to the input of the fourth switch 46, the output of which is connected to the second

the output of the computing device 16,

the ninth input of which is connected to the control input of the fourth switch 46.

To determine the power of the engine and the power loss in the transmission, the vehicle is set with driving wheels on the support rollers 1 and 2, press the Reset button 30, accelerate the vehicle to the speed of rotation of the engine controlled by the speed sensor 4. A signaling device 21 is turned on, which gives a light signal to disconnect the engine, disconnect the vehicle engine from the transmission's input shaft. In this case, the rotation of the transmission occurs in the mode of free coasting.

When the Reset button 30 is pressed, the RS-trigger on elements 2 AND-NO 27 and 28 is set to the zero state, i.e. at the first output of the RS flip-flop (output of the first element 2I-NOT 27) a logical zero is set. Acceleration of the vehicle begins without load (section I in Fig. 2). During acceleration, the output of the differentiator 14 generates a signal proportional to the acceleration Ј of the driving wheels of the vehicle, which is fed to the inputs of the third 33, fourth 34 and fifth 35 memory blocks of the computing device.

At the same time, signals to the inputs of the second 32 and first 31 blocks of memory are respectively received from the output of the normalizing converter 5 of the rotational speed sensor 4 and from the output of the normalizing converter 7 of the torque sensor 6. The second 32 and third 33 memory blocks are in recording mode, since the fourth input of the computing device 16 receives a logical unit signal from the output of the second element 2I 25, the outputs of which receive signals from the logical unit of the first comparator 8 and the RS-trigger (respectively the output of the second element 2I-NOT 28).

In the process of acceleration at time t ti, when the rotation frequency reaches the value of w, the first comparator 8 is triggered and a logical zero signal appears at the output of the first 2I element 25, which switches the second 32 and third 33 memory blocks to the storage mode. At their outputs there will be signals, respectively, and л1 corresponding to the moment of operation of the first comparator 8. At the same time, the first 31 and fourth 34 memory blocks go into recording mode, since the fifth input of the first device arrives at the fifth input of the computing device 16 element ZI 22, to the inputs of which signals of a logical unit are received, respectively, of the second comparator 9, inverter 23 (since after the first comparator 8 is triggered there will be a logic zero at its output) and an RS flip-flop (from the output of the second element 2I- NOT 28). The signal of the logical unit from the second output of the logic unit 15 is fed to the control input of the switch 19, which connects the output of the error amplifier 18 to the input of the power element control unit 20, which leads to the activation of the adjustable brake 3. From the time t c, the vehicle accelerates with additional load when the adjustable brake 3 is on (section II in FIG. 2).

When reaching a rotational speed of about 0) 2 at time t t2,

The second comparator 9 and at the output of the first element ZI 22 a logical zero signal appears, which puts the first 31 and fourth 34 memory blocks in the storage mode. The output of these memory blocks, respectively, will be signals corresponding to M0

And Ј2.

When the rotational speed o) s reaches, the third comparator 10 is triggered, which leads to a change in the state of the RS flip-flop, the appearance of a signal of a logical unit at the output of the second element ZI 24, which places the fifth memory block 35 in write mode. At the same time, at the fifth output of logic unit 15, a logical zero appears, and at the sixth, a logical unit turns on the signaling device 21, according to the signal to Disconnect the engine of which the vehicle engine is disconnected from the input shaft

transmissions. The vehicle enters the free run mode (section III, fig. 2). When the rotational speed a) is reached at the instant of time ts, the first comparator 8 returns to its initial state, and a logic zero signal appears at the input of the second element ZI 24, which translates the fifth memory block 35 into the storage mode. At the output of this memory block, a signal appears corresponding to a fc. At the same time, the logical unit 15 signal appears at the output of the logical unit 15 from the output of the second element 2И 26, since at both its inputs there are logical units from the output of the first comparator 8 and the output of the element 2И-27 27 of the flip-flop.

From the outputs of the third 33 and fourth 34 memory blocks, the signals are fed to the inputs of the first adder 36, the output of which

a signal is generated that is proportional to the difference Јi - Ј2. From the output of the first memory block 31 and the output of the first adder 36, the signals are fed to the inputs of the divider 37, at the output of which a signal is formed that is proportional to the particular M0 / (Ј h - Ј2). From the output of the divider, the signal is fed to the input of the sixth memory block 38, which is in recording mode, because at the eighth input of the computing device it finds the logical unit from the output of the second element 2I-HE 28 RS-flip-flop. From the outputs of the third 33 and sixth 38 blocks of memory, the signals arrive at the inputs of the first multiplier 39, the output of which forms a signal proportional to M0 Ј1 / (Ј1 - –Ј2). From the outputs of the fifth 35 and sixth 38 memory blocks, the signals are fed to the inputs of the second multiplier 40, the output of which produces a signal proportional to M0 Ј3 / (Јi Ј2). The signal from the output of the second multiplier is fed to the input of the first switch 41, which is in the open state up to the time point TK, since its control input receives a logical zero from the seventh input of the computing device 16. The signal from the output of the first multiplier 39 is fed to the first input adder 42. At the second input of adder 42, the signal comes from the output of the first switch 41. Thus, up to time tt3, a signal proportional to M0 Ј1 / (Ј1 - Ј2) is generated at the output of adder 42, and from time tt3 a signal proportional to M0 (Ј1 + Јz) / (Ј1 Ј2). The signal from the output of the adder 42 is fed to the input of the second switch 43, which is in the normally closed state due to the fact that its control input receives a signal from a logical unit from the normally closed contact of the fifth switch 47. The signals from the second switch 43 and the output of the second memory block 32 is fed to the inputs of the third multiplier 45 at the output of which a signal is generated until time t 13, proportional to the traction power at the wheels of the vehicle NK М0 Ј1 W / (Ј1 - --2), and after the times t t3 is a signal proportional to the engine power of the vehicle Md M0 to (Јi + Јs) w / (Јi - 3). The signal from the output of the third multiplier 45 is fed to the first input of the fourth switch 46, which

is in the open state since the moment of operation of the third comparator 10, when at the ninth input of the computing device there appears a logical unit from the first element 2I-NO 27 RS-flip-flop of the logic unit 15. Signal 0 0 5 5 5 5 0 5 U

five

the course of the fourth switch 46 is supplied to the recording device 17.

When the button n of the second switch 1 is pressed, the switch 47 receives the signal of the logical unit to the third switch 44 and the signal of the logical zero to the second switch 43. In this case, the signal from the output of the second adder 42 is output from the second input of the third switch 45 and the signal from the output of the first switch 41. At the output of the third multiplier 45, a signal is generated proportional to the power loss in the transmission and the NTp Mo V )3O) / (Ј1-)2) bench, which through the fourth switch 46 enters the recording device 17.

From the output of the second memory block 32, the signal arrives at the speed recording device 13, which reflects the speed at which the power is measured.

According to the values of engine power and power losses in the transmission and the bench, determined by the computing device 16 according to the above formulas, the technical condition of the vehicle is assessed.

Thus, in the proposed stand, two vehicle acceleration processes are repeated successively at two different load levels with subsequent free coasting, which eliminates the need to determine the inertia moment of the rotating mass of the transmission and the stand, reduces the load transient transient time and thereby improves the accuracy of diagnosis technical condition of the vehicle. Automatic determination of engine power and power loss reduces the complexity of diagnosis.

Claims (6)

Invention Formula T, Stand for diagnosing the technical condition of vehicles, containing supporting rollers mounted on the base, adjustable brake, kinematically connected to the support rollers, a rotational speed sensor of the supporting rollers with a normalizing converter, a torque sensor of the adjustable brake with a normalizing converter, a speed recorder , a differentiator, the input of which is connected to the output of the normalizing converter of the rotational speed sensor of the support rollers, the setpoint block, the first, second and the third comparators, the first inputs of which are connected respectively to the third, second and first outputs of the setpoint block, the second inputs of the comparators connect. with the output of the normalizing converter of the rotational speed of the support rollers, an automatic control system having an error amplifier, one input of which is connected to the output of the normalizing converter of the torque sensor of the adjustable brake, the second input - with the fourth output of the setpoint block, the switch, the first input of which is connected the output of the error amplifier, the control unit of the power elements, the input of which is connected to the output of the switch, and the output - to the input of the control element of the braking device, a signaling device, the input of which is connected to the output of the third comparator, a logic unit, the first, second and third inputs of which are connected respectively to the outputs of the first, second and third comparators, a computing device, the first input of which is connected to the output of the differentiator, the second input the output of the normalizing converter of the rotational speed sensor of the support rollers, the third input is with the output of the normalizing converter of the torque sensor of the adjustable brake, the fourth, fifth, w stand and seventh inputs - respectively with the first, second, third and fourth outputs of the logic unit, the registering device, the input of which is connected to the second output of the computing device, while the logic unit contains the first element 2I-NOT, the first input of which is connected to the third input of the logic unit , the second element 2I-NOT, the first input of which is connected to the output of the first element 2I-NO, the output to the second input of the first element 2I-NO, a resistor connected to the second input of the second element 2I-NOT and the positive terminal of the current source, a normally open contact connected to the second input of the second element 2I-NOT and the negative terminal of the current source, the inverter, element 2I, and with the aim that, in order to improve the diagnostics accuracy, the logic unit is equipped two ZI elements, the first input of the first ZI element is connected to the second input of the logic unit, the second input is connected to the output of the inverter, the input of which is connected to the first input of the logic unit, the third input to the output of the second element 2И-НЕ and the first input of the element 2И, the first input the second element ZI is connected to t The second input of the logic unit, the second input - with the output of the inverter, the third input - with the output of the first element 2I-NOT, the second input of the element 2I connected to the first input of the logic unit, the outputs of the element 2I, the first element ZI, the second element ZI and the second element 2I-NOT are connected respectively to the first, second, third and fourth outputs of the logic unit, the first output of the computing device is connected to the speed recorder. 2. The stand according to claim 1, wherein the computing device comprises five memory blocks, the input of the first block 0 memory is connected to the third input of the computing device, the input of the second memory block is connected to the second input of the computing device, the inputs of the third, fourth, and fifth memory blocks are connected and connected to the first input of the computing device, the control inputs of the second and third memory blocks these are connected to the fourth input of the computing device, the control input of the fifth 0 of the memory block is connected to the sixth input of the computing device, two adders, the inputs of the first adder are connected to the outputs of the third and fourth memory blocks, a divider whose inputs are connected 5 with the output of the first memory block and the output of the first adder, three multipliers, the first input of the first multiplier is connected to the output of the third memory block, the second input - with the output of the divider, the first input 0 of the second multiplier is connected to the output of the divider, the second input is with the output of the fifth memory block, the first input of the second adder is connected to the output of the first multiplier, the second input is with the second output of the second multiplier, the first input of the second memory block , the second input is with the output of the second adder, and the output is with the second output of the computing device, the output of the second memory block is connected to the first output of the computing device. 3. The stand according to claim 2, characterized in that, in order to increase stability 5 of the computing device, the sixth memory block is inserted into it, the first input of which is connected to the output of the divider, the output to the second input of the first multiplier and the first input of the second 0 multiplier, and the control input is connected to the seventh input of the computing device, which is connected to the fourth input of the logic block, which is connected to the output of the second element 2I-NOT. five 4. Stand on PP. 2 and 3, about tl and h and y y and i with so. that, for the purpose of convenience of reading information, the second element 2I is entered into it, the inputs of which are connected to the output of the first element 2I-NOT and the first input of the logic unit, and the output to the fifth the output of the logic unit, which is connected to the eighth input of the computing device, the output of the first element 2И-NOT is connected to the sixth output of the logic unit, which is connected to the ninth input of the computing device, two switches are entered into the computing device, the first input of the first switch is connected with the output of the second multiplier, the output with the second input of the second adder, and the control input with the eighth input of the computing device, the first input of the fourth switch is connected to the third output a multiplier, the output - to the second output of the calculation unit, and a control input - to a ninth input of a computing device. 5. Stand on PP. 2 and 3, that is, for the convenience of reading information, three switches are entered into the computing device, the first output of the normally closed contact of the fifth switch is connected to the control input of the second switch, the input of which is connected to the output of the second adder, and the output is connected to the second input of the third multiplier, the first output of the normally open contact of the fifth switch connected to the control input of the third switch, the first input of which is connected to the output of the second multiplier, and the output to the second input of the third multiplier, the second terminals of the acts fifth switch are combined and connected to the positive terminal of the current source. 6. Stand on PP. 4 and 5, that is, so that in the computing device the first input of the third switch is connected to the output of the first switch. F