SU1730724A1 - Image signal encoder - Google Patents

Abstract

The invention relates to computing. Its use in the construction of digital television systems makes it possible to increase the information content of the encoder by reducing the redundancy of the encoded signal. This is ensured by defining four different classes of coded blocks, each of which has its own algorithm for synthesizing the output codeword. The encoder contains an analog-to-digital converter 1, a block of 2 multipliers, blocks 3, 6 of summation, a node 5 of memory, a quantizer 4, a block of 7 inverting, an adder 8 modules, blocks 9-11 of a buffer memory, decoders 12, 13, blocks 14, 15 switching unit 16 coding. 4 hp f-ly, 4 ill.

Description

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The invention relates to computing and communications technology and can be used in the construction of digital television systems for the efficient encoding of television (TV) images.

The main requirement for efficient image coding systems is to ensure high image quality. At present, the practical task is the problem of fourfold compression of the flow, i.e. reducing the cost of coding an element to 2 bits / element. The best encoder that provides stream compression four times is the well-known variable-speed encoder. The encoder includes a prediction unit, a code converter, a buffer memory, and a transmitter. Depending on the filling of the buffer memory in the dynamics of operation and on the results of the analysis, the speed of signal processing in the prediction block and the code converter is automatically adjusted.

This encoder performs static coding of TV images, i.e. reversible coding and in principle does not lead to deterioration of image quality. Due to the nonstationarity of the source of TV images, the capacity of the buffer memory device turns out to be considerable — several frames.

However, the high hardware costs are a disadvantage of the indicated encoder.

The closest to the present invention is a device for encoding a television signal comprising an analog-to-digital converter (ADC), a memory unit, a multiplication unit, the first and second summation units, an inverting unit, a module adder, a quantizer, the first to third buffer registers, control symbol generator, first and second decoders, first-third switching units, first and second delay units, coding unit and BAN item.

The principle of operation of the device is as follows.

In an A / D converter, the input analog signal is converted to a digital video signal. In a memory block, a digital video signal from one field is stored and then sequentially read from a coding group with a dimension of 2x2 elements. For each coded group, three variable mean values of the luminance of the coding are calculated.

1 4 of this group Y x, where x, are elements

l, 1

the coded group, the half-sum of the modules of the deviations of the luminance of the olements of the coded

lai-x, l

from the average brightness of 32 and a binary matrix of digits of S with a dimension of 2x2, in which the units correspond to those elements xi that are greater than or equal to ai, and zeros to those elements to xi that are less than ai. The calculation of ai is performed by summation, the result of which is taken without the two least significant bits. The calculation of ar is similar to the calculation of ai with the only difference that the summation of the elements x; produced with an inverse value ai and the result of the summation is removed without one least significant bit.

The calculated values of ai and 32 quantized in a quantizer with a linear quantization scale, with seven bits of the output codeword being allocated for encoding ai.

In this device, the matrix of the sign function S | S × 2x2

L H J

It is transmitted in two bits, namely Si and $ 2 bits. Digits 5h and SA are excluded from transmission. On the receiving side, the excluded bits are restored as follows:

 0 | O 0. h o

eleven

Oh 0

0; o;

1h

where ;;, are the recovered bits of the matrix of the sign function.

Thus, the device excludes diagonal contours and lines, i.e. matrix of signs:

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1 1 | 11 Oi S 1 | 0 O

1 o | h lid o

U o

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 about 11 0 |, Go 1 1 about Jo ii d oi

When implementing this device, corresponding to the case of intraframe coding of groups of 2x2 elements, in which the number of quantization levels of the average luminance a is 128 (seven bits), the number of quantization levels of the half-sum difference 32 is 8 (three bits), the number of difference signs is two, The digital flow rate per element is 3 bits / element.

The transition from equal to the brightness section to the contour has a masking property, i.e. for the human eye, less noticeable inhomogeneities are equal to the capacitance near the contour. Therefore, exact seven-digit coding in the case of aai 0, aai-and 5 O, i.e. at the border is equal to the bright section - contour, it is redundant and in this case it can be coded more roughly ai into three bits. The texture in the image fragments also has a masking property, and therefore all the parameters of the coded groups can be coded more coarsely in the texture plots.

The presence of redundancy is a disadvantage of the prototype coder.

The aim of the invention is to increase the information content of the encoder by reducing the redundancy of the encoded signal.

This goal is achieved in that the image signal encoder contains an analog-to-digital converter whose input is the information input of the encoder, a multiplier unit whose outputs are connected to the inputs of the first summation unit, the first outputs of which are connected to the first inputs of the quantizer. The outputs of the analog-to-digital converter are connected to the information inputs of the memory node, the outputs of which are connected to the first inputs of the second summation block and the inputs of the block of multipliers. The second outputs of the first summation unit are connected via the inverting unit to the second inputs of the second summing unit, the outputs of which are connected to the second inputs of the quantizer through the module adder, the first to third outputs of which are connected to the information inputs of the first to third blocks of the buffer memory. The encoder also contains the first and second decoders, the first and second switching units, the first outputs of which are connected respectively to the first and second information inputs of the coding unit, the output of which is the output of the encoder. The first control inputs of the switching unit are combined, the first outputs of the second block of buffer memory are connected to the inputs of the first decoder, the output of which is connected to the second control input of the second switching unit. The first outputs of the third block of buffer memory are connected to the first information inputs of the second switching unit, the first information inputs of the first switching unit are connected to the first outputs of the third block of buffer memory, the second outputs of which are connected to the second information inputs of the first and second switching blocks, the second outputs of which are connected respectively to the third and fourth information inputs of the coding block. Third information inputs of the first switching unit

connected to the first outputs of the second block of the buffer memory, the second outputs of which are connected to the third information inputs of the second block

switching and inputs of the second decoder. The first outputs of the first block of the buffer memory are connected to the fifth information inputs of the coding block and the fourth information inputs of the second block

commutation. The second outputs of the first block of the buffer memory are connected to the sixth information inputs of the coding block and the fourth information inputs of the first switching unit, the second

the control input of which is combined with the seventh information input of the coding block and connected to the output of the first decoder. The output of the second decoder is connected to the first control input.

the second switching unit and the eighth information input coding unit. The first clock input of the image signal encoder is connected to the clock input of the ADC, the clock input of the memory node, the clock input of the quantizer and the first clock inputs of the first, second and third blocks of the buffer memory, the second clock inputs of which are connected to the first clock input of the coding unit and the second

a clock input of an image signal encoder, the third clock input of which is connected to the second clock input of a coding unit. The fourth clock input of the image signal encoder is connected to the synchronization input of the memory node.

The proposed device implements an adaptive group coding of TV images in 2x2 groups with the combination of groups in pairs into blocks. For each group of each block, three variables ai are calculated - the average brightness of the group; a - deviation from the average brightness; S - matrix

marks. In the prototype coder, seven bits are allocated for encoding ai, three bits for aa, two bits for S, which corresponds to compressing a video data stream to 3 bits / element.

In the proposed device, the entire set of image-forming fragments is divided into four classes. The division is made on the basis of an analysis of the values of a2i and 32 j, for the two groups forming the block.

If jaaa | t are equal to zero, then this block

corresponds to a class equal to the thickness of fragments (ai,) or fragments with melt

change of brightness (ai ats-n).

If 32 | 0, and 32 i + 1 0, this block corresponds to the transition from the equal section of the rectangular to the contour (the class is equal to the bright section of the contour). If 32 | 0, and 321 + 1 0, this block corresponds to the transition from the contour to the equal to the luminous section (the class of the contour is equal to the focal area). If 321 0, e 32 | +, 0, the block corresponds to the texture area (texture class).

For the determination, the transmitted unit belongs to the kzky class, in the output hexadecimal code word there are two service bits. The remaining fourteen information bits are distributed between the block groups depending on the block class. If this class is equal to the bandwidth level, then seven bits are allocated for transmitting 3g, and seven bits for transmitting ac + 1. If the block belongs to the class equal to the bony section-contour, then, taking into account the contour masking properties, the parameter av and equal to the capacitive group is transmitted more roughly by three bits, and in the contour group five bits are allocated to ai i +1, to 321 +1 Av bits, on Si + i - four bits. Fourteen information bits for the class contour are likewise allocated - equal to the luminous portion.

If the block belongs to a texture class, then, taking into account the texture masking properties, all parameters of the encoded groups are coded more coarsely. Three bits are assigned to au and ats + 1, two bits each to & 2 and 32 i + 1, two bits to Sj and Si + i. At the receiving side, the two bits excluded from the transmission of the sign function of each group are reconstructed so that the reconstructed matrix of signs corresponds to horizontal or vertical contours. The restoration of the matrix of marks in this way is due to the fact that the probability of the appearance of oblique contours in natural images is less than the probability of the appearance of horizontal or vertical contours. Human diagonal vision is less acute, therefore decoding errors are less noticeable in diagonal directions. Restoration of matrixes of signs is as follows:

1 CM JO Tr, 1 1; (0, 0m .1 O O 0 .1 llj

where chi.

- reconstructed matriV bits of the prototype encoder for encoding a block (i.e., two groups, 2 × 2)

Twenty-six bits were consumed; in the proposed device, sixteen bits were expended on coding a block. Adaptive approach in the distribution of information bits of the output code word for encoding the parameters of groups allows you to maintain a high subjective quality of the encoded images while reducing the digital stream from 3 bits / element to 2

0 bits / item.

At present, the main trend of developing algorithms for the efficient coding of TV images is an adaptive approach. Practically for everyone

Five known methods for compressing video information are proposed adaptive procedures for the formation of code words. For example, at the international exhibition GeBIT in Hannover (Germany), the Pons firm KK demonstrated a CP-200 universal processor that allows the following encoding programs to be executed: adaptive vector quantization (AVK); three-dimensional AVK; adaptive truncated block coding; adaptive discrete cosine transform; DPCM with adaptive quantization.

The proposed device also implemented adaptive coding, with

0 this is a two-step process: the first stage is the adaptive construction of the second decomposition function for each coded group; the second stage is an adaptive synthesis of the output code word and dependence on

5 class plot. The essential point of the device is the splitting of the coded blocks into classes with the adaptation of the encoding process to each class.

Known devices for group coding with independent coding of groups and partition of groups into classes.

In the listed devices, the classes are: equal areas, areas with a smooth change in brightness, a jump in the p5 bone and texture. Splitting into classes with independent coding of groups does not allow identifying the contours, i.e. portions of the image that come to be equal to the luminance group and the group with re-brightness. As a consequence, the coding accuracy of the contours turns out to be comparable with the coding accuracy of, for example, a brightness jump, i.e. when the neighboring group is not equal to the capacity. As a result, it is possible to restore the contours. When groups are combined into blocks, as is done in the proposed device, the contours are separated and for the groups with the contour a full character matrix is transmitted, i.e. contour directionality is maintained.

Two devices are known with grouping into blocks. In the first device, the matching between groups in the block is based on the statistical properties of the encoded plot, i.e. without regard to the limitations of visual perception. The second device also ignores the peculiarities of visual perception of images, since the developers' efforts are aimed at increasing efficiency by eliminating the coordinate redundancy of the encoded variables.

High quality of coded images during stream compression can be obtained only due to the maximum possible use of human visual analyzer properties. In the proposed device used the masking properties of the contours; texture masking properties; lower resolution of the eye in oblique directions than in horizontal and vertical, as well as the ability of the eye to average small luminance disturbances.

Fig. 1 shows a block diagram of an image signal encoder; in FIG. 2, the first (a) and second (b) switching unit circuits; FIG. 3 shows a memory node, an exemplary embodiment; Fig. 4 is a buffer storage unit, an exemplary embodiment.

The image signal encoder contains analog-to-digital converter 1, whose input is the information input of the encoder, block 2 of multipliers, the outputs of which are connected to the inputs of the first summation block 3, the first outputs of which are connected to the first inputs of the quantizer 4. The outputs of analog-digital converter 1 are connected to the information inputs of the memory 5, the outputs of which are connected to the first inputs of the second summation block b and the inputs of the block 2 multipliers. The second outputs of the first summation unit 3 are connected via the inverting unit 7 to the second inputs of the second summation unit 6, the outputs of which through the adder 8 modules are connected to the second inputs of the quantizer 4, the first to third outputs of which are connected to the information inputs of the first 9 to third 11, respectively. buffer memory. The encoder also contains the first 12 and second 13 decoders, the first 14 and second 15 switching units, the first outputs of which are connected respectively to the first and second information inputs of the coding unit 16, the output of which is the output of the encoder.

Analog-to-digital converter (ADC) 1 is made according to the well-known scheme

five

0

a separate analog-to-digital converter with encoding logic on the permanent memory. In a block of 2 multipliers, each element is multiplied by 1 / n. Block 2 can be implemented on a LPR, each of which receives one element xi. In the EPROM, in accordance with the wired multiplication program, xi is multiplied by 1 / n. In order to increase the multiplication accuracy, block 2 can be implemented on D-registers and several summation circuits, which allow to carry out the multiplication operation by summing the corresponding signals.

The first 3 summation block contains the actual summation schemes performed on the AND, OR, and NOT gates. For four simultaneously coded elements, block 3 contains three summation schemes: on the first one it adds up and

X2HZH4P

- on the second -jp and -jp and on the third - the sum of the first and second summation schemes. Quantizer 4 contains a converter of codes that can be implemented on an EPROM, and delay blocks that can be executed, for example, on D-triggers or logic elements. Roughness is produced in converters

A uniform quantization of an eight-bit code 32 to a three-bit 32 according to rule 32 32/32, which uniquely identifies the code converter recoding table.

The memory unit 5 includes a buffer register 26, a first pulse counter 22, a second pulse counter 23, a converter of 24 codes, a multiplexer 25 of a random access memory 21, made, for example, on a 565RU5 chip. To image 512x512 elements, the first 22 and second 23 pulse counters are eighteen-bit, i.e. an 18-bit address is generated. 24 code converter

5 (e.g., at PT5) is also eighteen bits. The multiplexer 25 can be performed on the logical elements AND, OR, NOT.

The second block 6 summation contains

0n summation schemes. The i-th summation scheme 0 1, p) calculates the sum Xi with (-ai), i.e. computed di xt - ai -xi + ai + 1, where zi comes from the output of inversion block 7, which is

5 block inverters. The values of di are transmitted to the adder 8 modules, which for p 4 consists of four EPROM circuits and three adders. The i-th scheme of the EPROM receives di, in which the translation program d is wired (from the supplemental to the direct code, i.e. essentially

0

The calculation of the module di. In the first summation scheme, Idil and Id2l are added, in the second, Idal and Id4l, in the third, the sums from the outputs of the first and second summation schemes

neither 32 tt 2 I xi - ai I. Calculated i 1

the amount without the least significant bit (i.e., divided by 2) is output. In addition, 8 modules provide the output of the adder with a matrix of characters, which is calculated when determining the Ixrail modules. The codes ai, az, and S enter the quantizer 4.

The image signal encoder contains the first 14 and second 15 switching units, the first control inputs of which are combined, the first outputs of the second buffer storage unit 10 are connected to the inputs of the first decoder 12, the output of which is connected to the second control input of the second switching unit 15, The first outputs of the third the buffer memory unit 11 is connected to the first information inputs of the second switching unit 15. The first information inputs of the first switching unit 14 are connected to the first outputs of the third block 11 of the buffer memory, the second outputs of which are connected to the second information inputs of the first 14 and second 15 switching units, the second outputs of which are connected to the third and fourth information inputs of the coding 16, respectively. The third information inputs of the first switching unit 14 are connected to the first outputs of the second buffer storage unit 10, the second outputs of which are connected to the third information inputs of the second switching unit 15 and the inputs of the second decoder 13. The first outputs of the first buffer storage unit 9 are connected to the fifth information inputs of the coding unit 16 and the fourth information inputs of the second switching unit 15. The second outputs of the first buffer memory unit 9 are connected to the sixth information inputs of the encoding unit 16 and the fourth information inputs of the first switching unit 14, the second control input of which is combined with the seventh information input of the encoding unit 16 and connected to the output of the first decoder 12. The output of the second The decoder 13 is connected to the first control input of the second switching unit 15 and the eighth and information input of the encoding unit 16. The first clock input of the image signal encoder is connected to the clock input of the ADC 1, the clock input of the memory node 5, the clock input of the quantizer 4 and the first

clock inputs of the first 9, second 10 and third 11 buffer memories, the second clock inputs of which are connected to the first clock input of the coding unit 16 and the second clock input of the image signal encoder, the third clock input of which is combined with the second clock input of the coding block 16. The fourth clock input of the image signal encoder is connected to the synchronization input of the memory node 5.

The first buffer memory block 9 contains the first 27, second 28 and third 29 buffer registers, which are three seven-bit parallel registers. The inputs of the first 27 and third 29 registers are interconnected and connected to the first outputs of the quantizer 4. The output of the first register 27 is connected to the inputs of the second register 28. The first register 27 is clocked by the frequency fraKT, and the second 28 and the third by the 29 frequency fraKT / 2, which allows At the outputs of the second 28 and third 29 registers, it is possible to receive simultaneously the codes ai and ats + 1 of average luminance from the subsequent group.

The second block 10 of buffer memory is similar in device to the first, with the only difference being that two-bit registers are used instead of seven-bit ones, the third block of buffer memory 11 in device is similar to the first one with the only difference that four-bit ones are used in place of seven-bit ones parallel registers.

The decoders 12 and 13 are made on the elements OR-2NE.

The first switching unit 14 comprises the first 17 and second 18 multiplexers, the first and second control inputs of which are respectively combined and are the same inputs of the block. The first information inputs of the first 17 and second 18 multiplexers are respectively combined and are the third information inputs of block 14. The second information inputs of the second multiplexer 18 are respectively combined with the second and third information inputs of the first multiplexer 17 and are the fourth information inputs of block 14. The fourth information inputs of the first

17 and third information inputs of the second

The 18 multiplexers are respectively combined and are the second information inputs of block 14. The fourth information inputs of the second multiplexer 18 are the first information inputs of block 14. The outputs of the first 17 and second 18 multiplexers are

respectively, the first and second outputs of block 14.

The second switching unit 15 contains the first 19 and second 20 multiplexers, the first and second control inputs of which are respectively combined and are the same inputs of block 15. The first information inputs of the first 19 and second 20 multiplexer are combined and are the first inputs of the second switching unit 15 , the second information inputs of which are connected to the second inputs of the second multiplexer 20, the third inputs of which are combined with the second and third inputs of the first multiplexer 19 and are the fourth information inputs Lok switch 15, the third informational inputs of which are connected to fourth inputs of the first 19 and second multiplexers 20, outputs of which are per- Vym and second outputs of the second switching unit 15,

Multiplexers 17 and 18 are two four-to-one multiplexers that are controlled by two control signals. Multiplexers 19 and 20 are similar to multiplexers 17 and 18.

Coding unit 16 contains a parallel-serial D-register.

The control of the blocks included in the coder is performed by a synchronous generator (not shown). The synchronous generator generates the following frequencies: fT - clock, frequency of fr / 2 group, channel TK, field frequency fn.

The image signal encoder operates as follows.

An analogue television signal is fed to the input of ADC unit 1, which is converted into a digital video signal. In the memory node 5, as a result of the delay of the digital signal for the time of one field, a series of digital signals are created, each of which corresponds to one of the aperture elements of a 2x2 element (i.e., a group of adjacent image elements). After multiplying in block 2 by weights in the first block 3 summation, the average value of the luminance over the coded group is calculated (coefficient ai). In the second block, B, the sum of the luminance by group is calculated from the luminance value of each element of the group (i.e., blocks 7 and 6 functionally form a subtractor). In the adder 8 modules, the sum of the modules of the differences obtained in block 6 is added. The calculated sum without the least significant bit (i.e., divided by 2) is output. In addition, a matrix of characters is calculated at the output of the adder 8 modules, calculated at

defining the modules lxi-ail. Codes ai, 32 and 3 enter the quantizer.

From the first outputs of the quantizer 4, a seven-bit code ai is fed to the inputs of the first block 9 of the buffer memory. From the second outputs of the quantizer 4, the two-digit code 32 is fed to the inputs of the second block 10 of the buffer memory, from the third outputs of the quantizer 4 the four-digit code S is fed to the inputs of the third block 11 of the buffer memory.

The first block 9 of the buffer memory contains three seven-bit parallel buffer registers. The inputs of the first and third buffer registers are interconnected and are the inputs of the first block 9 of the buffer memory. The outputs of the first buffer register are connected to the inputs of the second buffer register. The outputs of the second and third buffer register are outputs of the first buffer memory unit 9. The first and second buffer registers are clocked with the frequency fr, and the third with the frequency fT / 2. The ai code goes to the inputs of the first and third registers. With clock pulses, code ai is rewritten from the first buffer register to the second. At the output of the second buffer register, the code ai will be only after a time equal to two periods of the clock frequency. During this time, other parameters of the coded group are computed, i.e. AC-C, 32i + i, SH-L The AC + 1 code is fed to the inputs of the first and third buffer registers at the moment the code ai is present at the inputs of the second buffer register. With pulses with a frequency of the contact code aii and pulses with a frequency of fr / 2, the code ac + 1 is simultaneously written to the outputs of the second and third registers, i.e. on the two outputs of the first 9 and the block of buffer memory there are seven-bit codes ac and ac + 1 from the next coded group.

Similarly to the first block 9 of the buffer memory, the second 10 and third 11 blocks of the buffer memory work. At the two two-bit outputs of the second block 10 of the buffer memory there are simultaneously codes 32 | and 32,.,. The two four-bit outputs of the third block 11 of the buffer memory simultaneously contain codes Si and S (+ i.

The first 12 and second 13 decoders analyze the fragment of the image to which the group of encoded elements belongs. The inputs of these decoders are codes 32; and 32, + ,. If the coded groups belong to the equal portion of the image, i.e. all elements in the 2x2 group are equal, then the values 32 | and aa j, f are zero and

signals at the outputs of the decoders 12 and 13

zeros. If the coded groups belong to the texture section, then for such groups the values are aa (AND 32 j, are nonzero and the signals at the outputs of the decoders 12 and 13. Units. If the image fragment corresponds to the transition from equal to the bright section to the contour, then for the group is equal to the bright section 32 (0, and for the group corresponding to the contour, E21g1 0. Signals on

the output of the decoder 12 - O, at the output of the decoder 13 - 1. If the fragment of the image corresponds to the transition from the contour to the equal to the bright section, then 32j 0; 32 -f f 0 and the signals at the decoder outputs

Ditch 12 and 13 - 1 and O, respectively.

Thus, a combination of output or control signals from the decoders determines the type of fragment being encoded. If the combination of control signals 00, then the encoded fragment corresponds to a luminous region or a region with a smooth change in luminance. If the combination of control signals 11, then the encoded fragment corresponds to the texture, and if the combination of control signals is 01 or 10, then the encoded fragment corresponds to the transition equal to the luminous portion — the contour or circuit — equal to the luminous portion.

From the second outputs of the first block 9 of the buffer memory, the seven-digit code a ai;

is supplied as follows: the three most significant bits of the code ai are supplied to the fourth inputs of the encoding unit 16, and four bits are supplied to the fifth inputs of the first switching unit 14. In the switching unit 14, the two lower bits of the code ai | served on

the second inputs of the second multiplexer 18, and the two remaining bits are supplied to the second and third inputs of the first multiplexer 17.

From the first outputs of the first block 9 of the buffer memory. seven-bit code aii + i

served as follows: the three most significant bits of the code ai i + 1 are fed to the third

the inputs of coding unit 16, and four bits are supplied to the fourth inputs of the second switching unit 15. In switching unit 15, the two low bits of the code ai, 4-- are fed to the fourth inputs of the second multiplexer 20, and the two remaining bits are fed to the third and fourth inputs of the first 19 multiplexer.

The control bit from the output of the first 12 decoder is fed to the first input of the first switching unit 14, to the fifth input of the second switching unit 15 and to the fifth

five

d

five

0

0

five

n 5

the input unit 16 encoding. In switching units 14 and 15, the control bit is fed to the first inputs of the multiplexers 17-20.

The control bit from the output of the decoder 13 is fed to the second input of the second block

15 switching to the fourth input of the first switching unit 14 and to the second input of the block

16 encoding. In switching units 14 and 15, this control bit is fed to the second inputs of multiplexers 17-20.

From the first outputs of the second 10 block of the buffer memory, the two-digit code 32j is supplied to the third inputs of the first switching unit 14. In this block, the two-digit code is 32 | fed to the first inputs of the first

17 multiplexer and the first inputs of the second multiplexer 18.

From the second outputs of the second block 10 of the buffer memory, a two-digit code a a2i -) - 1

is supplied to the third inputs of the second switching unit 15. In this block, a two-bit code aa j-f,) is fed to the first inputs of the first multiplexer 19 and to the first inputs of the second multiplexer 20.

From the first outputs of the third block 11 of the buffer memory, the four-digit code Si is supplied to the first inputs of the second switching unit 15. Two bits of the four-bit code Si are supplied to the second inputs of the first switching unit 14. In switching unit 14, two bits of the code Si are supplied to the fourth inputs of the first multiplexer 17 and the same bits of the code Si are fed to the second inputs of the second 20 multiplexer of the second switching unit 15. The other two bits of the Si code in the switching unit 15 are supplied to the second inputs of the first multiplexer 19.

From the second outputs of the third block 11 of the buffer memory, the four-bit code Si + is routed to the second inputs of the first switching block 14. Two bits from the four-bit Zn-1 code are supplied to the second inputs of the second switching unit 15. In switching unit 15, the two bits of the code Si + i are fed to the third inputs of the second multiplexer 20, and the same bits of the code Sj are fed to the second and third inputs of the second multiplexer 18 of the first switching unit 14. Two other bits of the code Si + i in the switching unit 14 are supplied to the fourth inputs of the first multiplexer 17.

The structure of the output codeword of the image signal encoder depends on the type of image fragment being encoded. If the fragment being encoded is a texture, then in two adjacent groups of 2x2 codes 32, and 32 j-f are different from zero. Control signals at the outputs of the decoders 12

and The combination of control signals 11 commutes to the first outputs of the first switching unit 14 two bits of code 32 | by switching to the outputs of the first multiplexer 17 of its first inputs. Two bits of the Si code are switched to the second outputs of block 14 by combination 11 by switching to the outputs of the second multiplexer 18 of its fourth inputs.

The combination of control signals 11 commutes to the second outputs of the second switching unit 15 two bits of code 32 i + 1 by switching to the outputs of the first multiplexer 19 of its first inputs. The first outputs of block 15 by combination 11 commute two bits of code Si + 1 by switching to the outputs of the second multiplexer 20 of its third inputs.

Thus, if the encoded fragment is a texture, then ai | - the average brightness of the coded group — represented by three bits; aai — deviation from average luminance — is represented by two bits; Si, the sign matrix, is represented by two bits. For the neighboring group, ai j + i is represented by three bits; 32 i + 1 - two digits; Si + 1 - two bits.

If the encoded fragment is equal to the luminous area or the area with a smooth change in brightness, then in two adjacent groups of 2x2 E2 codes | and 321 +1 are zero. The control signals at the outputs of the decoders 12 and 13 are O. The combination of the control signals 00 commutes to the first outputs of the first switching unit 14 two bits of the code aij by switching to the outputs of the first multiplexer 17 of its third inputs. Two lower bits of the aij code are switched to the second outputs of block 14 by a combination of 00 by switching to the outputs of the second multiplexer 18 of its second inputs.

The combination of control signals 00 commutes to the second outputs of the second switching unit 15 two bits of the ac + 1 code by switching to the outputs of the first multiplexer 19 of its fourth inputs. Two lower bits of the code 311 + 1 are switched to the first outputs of block 15 by a combination of 00 by switching the outputs of the second multiplexer 20 of its fourth inputs to the ne.

Thus, if the encoded fragment represents a region with a smooth change in luminance or is equal to the luminance region, then aij is the average brightness value

five

0

five

0

five

0

five

0

five

my group is represented by seven bits and 311 +1 by seven bits.

If the fragment being encoded is a transition from the equal to the loudness section to the contour, i.e. Since one coded group belongs to the equal-length segment, and the other group to the contour, then in the first group a2 | 0, and in the second E2 | + 1 - 0. The control signal at the output of the decoder 12 - O, at the output of the decoder 13 - 1. Combination of the control signals 01 comm pyei to the first outputs of the first switching unit 14 two bits of the code Si + 1, by switching to the outputs of the first multiplexer 17 of its fourth inputs. Two other bits of the code Si are switched to the second outputs of block 14 by combination 01 and by switching to the outputs of the second multiplexer 18 of its third inputs.

The combination of control signals 01 commutes to the second outputs of the second switching unit 15 two bits of the code ai i + 1 by switching to the outputs of the first multiplexer 19 of its third inputs. The first outputs of the switching unit 15 by the combination 01 commute two times of the code E21 + 1 by switching the outputs of the second multiplexer 20 of its first inputs to the outputs.

Thus, if the encoded fragment is a transition from an equipotential section to a contour, then for equipotential section, aij is represented by three bits, and for a contour group, ai | + 1 5 bits; a2j +1 - two bits; ; SI-H - four bits, which allows for more accurate1 encoding contours.

If the encoded fragment is a transition from the contour to the equal to the luminous region, i.e. one coded group belongs to the contour, and the other group belongs to the capacitance section, then in the first group E2, 0- and in the second group 32 i + i 0. The control signal at the output of the decoder, at the output of the decoder 13 - O. signals 10 commutes to the first outputs of the first switching unit 14 two bits of the aij code by switching to the outputs of the first multiplexer 17 of its second inputs. On the second outputs of block 14, the combination 10 commutes two bits of the E2 code | by switching to the outputs of the second 18 multiplexer of its first inputs.

The combination of control signals 10 commutes to the second outputs of the second switching unit 15 two bits of code

Si by switching to the outputs of the first multiplexer 19 of its second inputs. The first outputs of switching unit 15 are switched by a combination of 10 two bits of the Si code by switching to the outputs of the second multiplexer 20 of its first inputs.

Thus, if the encoded fragment is a transition from the contour to the equal to the luminous section, then for the group of the contour, ai is represented by five bits, aag by two bits, Si - by four bits, and for the group is equal to the bright section, three digits.

In coding block 16, the parallel code arriving at its eight inputs is minimized to a serial and output to the encoder output bit by bit.

When implementing the proposed device, corresponding to the case of intraframe coding of groups of 2x2 elements, the flow of a digital stream for information about one element is 2 bits per element. Compared to the prototype, the gain in stream compression is 1 bit / element. The manufacturing cost of the proposed device is almost the same as that of the prototype coder, since the effect is achieved as a result of the introduction of new connections. In this case, the cost is paid off by the gain in expensive bandwidth of the communication channel, which is achieved as a result of a decrease in the video data stream.

Claims (5)

1. An image signal encoder containing an analog-to-digital converter whose input is an information input of an encoder, a multiplier unit whose outputs are connected to the inputs of the first summation unit, the first outputs of which are connected to the first inputs of a quantizer, the outputs of the analog-digital converter are connected to information inputs of the memory node whose outputs are connected to the first inputs of the second summation block and inputs of the multiplier block, the second outputs of the first summation block through the link inverting block They are not connected to the second inputs of the second summation unit, the outputs of which are connected via the adder of modules to the second inputs of the quantizer, the first and third outputs of which are connected to the information inputs of the first and third blocks of the buffer memory, the first and second decoders, the first outputs of which are connected respectively to the first and second information inputs of the coding unit, the output of which is the output of the encoder, the first control inputs of the switching units are combined, the first outputs in The first block of the buffer memory is connected to the inputs of the first decoder, the output of which is connected to the second control input of the second switching unit, the first outputs of the third block of the buffer memory are connected to the first information inputs of the second switching unit, in order to increase the information content of the encoder account of redundancy reduction of the encoded signal, first the information inputs of the first switching unit are connected to the first outputs of the third block of the buffer memory, the second outputs of which are connected to the second The information inputs of the first and second switching units, the second outputs of which are connected respectively to the third and fourth information inputs of the coding unit, the third information inputs of the first switching unit are connected to the first outputs of the second buffer storage unit, the second outputs of which are connected to the third information inputs of the second switching unit the inputs of the second decoder, the first outputs of the first block of the buffer memory are connected to the fifth information inputs of the coding block and the fourth information second inputs of the first switching unit, the second outputs of the first switching unit, the second control input of which is combined with the seventh information input of the encoding unit and connected to the output of the first decoder, the output of the second decoder connected to the first control input of the second switching unit and the eighth information input of the coding unit, clock inputs of the analog-to-digital converter, the memory node and the quantizer and the first clock inputs of the first to third blocks of the buffer memory are combined and are the first clock input of the encoder, the second clock inputs of the first to third blocks of the buffer memory and the clock input of the encoder are the second clock input of the encoder, inputs synchronization of the coding block and the memory node are respectively the first and second clock inputs of the encoder, the control inputs of the RAM block are the same inputs of the encoder. 2. A coder according to claim 1, characterized in that the first switching unit comprises first and second mutiplexers, the first and second control inputs of which are respectively combined and are single-input inputs of the unit, the first information inputs of the first and second multiplexers, respectively, are combined and The third information inputs of the block, the second information inputs of the second multiplexer, respectively, are combined with the second and third information inputs of the first multiplexer and are the fourth information inputs in the block moves, the fourth information inputs of the first and the third information inputs of the second multiplexer are respectively combined and are the second information inputs of the block, the fourth information inputs of the second multiplexer are the first information inputs of the block, the outputs of the first and second multiplexers are the first and second outputs of the block respectively. 3. The encoder according to claim 1, characterized in that the second switching unit comprises first and second multiplexers, the first and second control inputs of which are respectively combined and are single input blocks, the first information inputs of the first and second multiplexer are the first inputs of the second switching unit, the second information inputs of the second multiplexer are the second information inputs of the block, the third inputs of the second multiplexer respectively are combined with the second and third inputs of the first mu the multiplexer and are with the fourth information inputs of the block, the fourth information inputs of the first and second multiplexers are respectively combined and are the third information inputs of the block, the outputs of the first and second multiplexers are the first and second outputs of the block respectively. 4. An encoder in accordance with claim 1, characterized in that the memory node contains a memory block, first and second pulse counters, a code converter, a multiplexer and a buffer register, whose information inputs are node information inputs, a clock input of the buffer register combined with the counting inputs of the pulse counters and the control input of the multiplexer are the clock input of the node, the zero inputs of the pulse counters are combined and are the synchronization input of the node, the outputs of the buffer register are connected to the information The inputs of the main memory unit, the control inputs of which are the inputs of the node, the outputs of the first pulse counter are connected to the first information inputs of the multiplexer, the outputs of the second pulse counter are connected to the second information inputs of the multiplexer, the outputs of which are connected to the address inputs of the block memory whose outputs are node outputs. 5. An encoder according to claim 1, characterized in that the buffer memory block contains first to third buffer registers, the information inputs of the first and third buffer registers are respectively combined and are the information inputs of the block, the outputs of the first buffer register are connected to the information inputs of the second buffer register The outputs of which and the outputs of the third buffer register are respectively the first and second outputs of the block, the clock input of the first buffer register is the first clock input of the block, clock inputs of the second The left and third buffer registers are combined and are the second clock input of the block. 7 4G7L + i V k and h i i ii Ohno 14 C 4 nineteen VV . i3 Fig 3 a 18 v eleven 15 ii 20 P L 26 21 21 ff L jt Z1 28 Phie, 4 7 29