SU1730625A1 - Device for multiplying of s-digits in radix-residue number system - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-performance devices operating in the position-residual number system. The purpose of the invention is to reduce hardware costs. A device containing two switches 14, 15, two blocks of constant storage 1.2, two blocks 5, 6 multiplications, a first delay element 7, six blocks 8-13 and elements And two adders 3, 4, a second delay element 26 is inserted, two registers 24 and 25 and two multiplexers 22 and 23, which made it possible to remove two multiplication units from the structure of the device, the volume of which is many times the volume of the entered blocks. 3 il.

Description

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The invention relates to computing and can be used to build high-speed arithmetic devices operating in a positional-residual system.

The purpose of the invention is to reduce hardware costs.

Fig, 1 shows a functional diagram of the device; in fig. 2 - time diagram of current signals; in fig. 3functional multiplexer circuit.

The device contains two blocks 1 and 2 of storage of constants, two adders 3 and 4, two blocks 5 and 6 multiplication, the first delay element 7, six blocks 8-13 of the elements I, two switches 14 and 15, the inputs of the first 16 and second 17 operands of the device , the first 18 and second 19 clock inputs of the device, the outputs of the older 20 and younger 21 bits of the device, two multiplexers 22 and 23, two registers 24 and 25, the second delay element 26 and the third 27 clock input of the device.

The basis for the operation of the device for multiplying 3 digits in the position-residual number system is the following.

We write the product of two 3-digit in the form

a-b (ai V1T + a0) (bi VlT + bo)

 aibr S + a0bi + aib0

+ a0bo flS1 + foS0,

We write the second and third term in the form

aobiS. aiboS

 + c0 + diS1 + do,

where fi aibi + ci + di; to a0b0 + Co + do

a0 rest (a / vs); ai ent (a /); b0 rest (b / VTj: bi ent (); c0 rest (a0bi /); ci ent (a0bi / VS); d0 rest (aib0 /); di ent (aib0 / VSl, where rest (X / Y) is the remainder dividing X by Y;

five

0

50

five

0

five

0

five

0

five

ent (X / Y) is the integer quotient of dividing X by Y.

It is known that the numbers in the 3rd position-residual number system are represented modulo-system (JU) in the form

a ("1, aiak);

B (,)

where "| rest (a / pj);

(b / pj);

j 1, K;

Pj - modules SOK, satisfying the acceleration

the clause P Pj - 23 (prime numbers), j 1

For consistency with devices operating in the binary number system, S 2m is usually chosen in position-residual devices. It is most convenient to accept m 8 and accordingly 3 28 256, and among the modules JUICE to have one, equal to VS. In the particular case, let Pi V256 16. This allows for the hardware implementation of blocks 1 and 2 of the storage of constants to obtain economical solutions.

The device for multiplying 3 digits in the position-residual numbering system works as follows.

On the first clock signal coming to the device at input 18, A

 ("1," 2 "k) and B (, / fc / k),

represented by code SOK modulo m Pi,

2 Рк, on entrances 16 and 17 arrive on.

switches 14 and 15, from the outputs of which are transmitted to the inputs of the corresponding blocks 1 and 2 of storing constants. These blocks are constructively constituting blocks of 21 bit words.

to

each where I j j is binary bit j 1

the deductibility of a or D- In these blocks, in accordance with expression (3), the values ai, ao and bi, bo are formed, respectively. The value a from the first output of the storage unit 1 through the first information input of the first multiplexer 22 is fed to its output, from which it goes to the first input of the first multiplication unit 5, to the second input of which from the first output of the second constant storage unit 2 enters bi. Simultaneously, the second output of the first storage unit 1 of the constants ao is fed to the first information input of the second multiplexer 23, the first open input of the second multiplication unit 6, the second input of which from the second output of the storage unit 2 of the constants receives the value of 0. From the output of the first multiplication unit 5, the quantity a0b0 goes to the first input of the second block 9 elements I, which passes into the first adder 3. From the output of the second multiplication unit 6, the value a0bo goes to the first input of the fifth block 12 elements And, passed that in the second adder 4. After some time, the device receives the third clock signal at input 27 (see Fig. 2). On this signal, the first information inputs of the multiplexers 22 and 23 are closed and their second information inputs are opened. At their outputs, the values of ao and ah appear, respectively, arriving at the first inputs of blocks 5 and 6, respectively, of the multiplication, the second inputs of which receive the values of b and b. At the outputs of blocks 5 and 6 of the multiplication, the values of a0bi and aibo are formed, which, by the third clock signal delayed on delay element 26, are entered into the first 24 and second 25 registers, respectively. After that, the first at input 16 and the third at input 27 of the clock signals are removed. This ends the first cycle of the device.

The second cycle of operation of the device begins with the removal of the first 18 and third 27 clock inputs of the signals and applying the signal to the second clock input 19 of the device (Fig. 2). By this signal, the values a0bi and aibo through the switches 14 and 15 pass to the inputs of blocks 1 and 2 storage constants, on the first and second outputs of which cico and dido values are formed. By this time, the second clock signal delayed by the first delay element 7 opens the second inputs of the block 8, 10, 11 and 13 elements AND, the first inputs of which from the outputs of the first 1 and second 2 constant storage blocks receive the values ci, di, Cp, do and, having passed them, go to the corresponding adders 3 and 4. As a result, in these adders, the highest and the youngest 3rd bits of the product of 3 digits in the position-residual number system are formed.

Claims (1)

The invention The device for multiplying Sx digits in the position-residual number system, containing two blocks of storing constants, two switches, two blocks of multiplication, the first delay element, six blocks of elements And two adders whose outputs are connected respectively to the outputs of the high and low bits the device, the inputs of the first and second operands of which are connected respectively to the information inputs of the first groups of the first and second switches, the first control inputs of which are connected to the first clock input of the device and the first inputs of the AND elements of the first and The second blocks, the second inputs of which are connected respectively to the outputs of the first and second multiplication blocks, the outputs of the first and second switches are connected respectively to the inputs of the first and second 0 storage units of constants, the first output of the first storage unit of the constants is connected to the first inputs of the elements of the third block, the second inputs of which are connected to the first inputs of the elements of the fourth, 5 fifth and sixth blocks and the output of the first delay element, the input of which is connected to the second control inputs of the first and second switches, the second output of the first storage unit of constants is connected 0 with the second inputs of elements I p of the unit, the first output of the second storage unit of constants connected to the input of the first multiplier of the first multiplication unit and the second inputs of elements of the fourth block, the second output of the second storage unit of the constants connected to the input of the first multiplier of the second multiplication unit and second inputs elements And the sixth block, the outputs of the elements And the third, first and fourth 0 blocks are connected respectively to the inputs of the first, second and third components of the first adder, the outputs of the elements And the fifth, second and sixth blocks are connected respectively to the inputs of the first, second 5 and the third component of the second adder, characterized in that, in order to reduce hardware costs, two multiplexers, two registers and a second delay element are introduced into it, the output of which 0 is connected to the control inputs of the first and second registers, the outputs of which are connected to the information inputs of the second group of the first and second switches, respectively, and the information inputs 5, respectively, to the outputs of the first and second multiplications blocks, the inputs of the second factors, respectively, the first control inputs of which 0 is connected to the first clock input of the device, the third clock input of which is connected to the input of the second delay element and the second control inputs of the first and second multiplexers, the information inputs of the first group of which are connected to the first output of the first storage unit of constants, the second output of which is connected to information inputs of the second group of the first and second multiplexers. /eight 27 1Q 1 L Fig 27 :) do (Cr) C09 18 d, (d0) About OS; (C0) r r r r r i I Shp} do№) FIG 3 a161, aQ-60 Qo-Bj. a1 -B0 CrCo.dj