SU1721760A1 - Method of controlling three-phase regulated bridging transformer - Google Patents

Abstract

The invention relates to electrical engineering. The aim of the invention is to improve the spectral composition of the output voltage of the converter in the process of coupled smooth control of the frequency and value of the output voltage. The control method is to periodically turn on and off with a mutual phase shift of 60 al. Primary valves The invention relates to electrical engineering and can be used to control adjustable transducers for electric drives based on thyristor voltage inverters. Algorithms for controlling semiconductor converters are known that provide an improvement in the shape of the output voltage curve due to multiple additional switching of valves. However, the regulation or stabilization of the output voltage in a fairly wide range requires the presence of a controlled inverter lee at the input of the inverter, with the conduction intervals and the closed state of the valves being 100 electr. In the middle of the intervals spent on the clock intervals of 60 degrees, asymmetrically in the middle of the half-period, control signals are turned off for the valves, the number of which at the initial output frequency F0 is equal to n. To achieve the goal in the output frequency range F0-Fon / 2, the output frequency is controlled by - i converter yarns are carried out due to the continuous stepwise variation of the pause durations between the control pulses located inside the central sections of the left and right parts of the said event intervals lasting 24 el.grad. each, as well as the duration of the neighbors on the left to the centers of the said 24-degree parts of the control signals. In the middle of each clock interval, additional control signals with a duration of 12 hl will form opposite to the corresponding control zone. 4 il. rectifier, which reduces the total efficiency of the process of electricity conversion and increases the negative impact of converters on the supply network. The algorithm of key management of thyristor circuits WID-1 is also known, in which at the initial frequency Fo the middle of the conduction zones and the closed state of each of the six inverter gates (clock intervals of the conduction and closed state) are divided into n sections (subintervals), in the right the extreme parts of each of which form respectively the main pauses and the conduction sections fe 4 Yu 1

Description

of a new duration, the duration of which determines the magnitude of the output voltage of the inverter.

However, the spectrum of such output curves contains low-order parasitic harmonic components of considerable order, among which the fifth harmonic is the most difficult to remove. In addition, the provision of a rational mode of operation of the converters loaded on asynchronous motors and frequency controlled over a wide range, accompanied by a consistent decrease in the number of output pulses in the output half-wave, is abrupt, which leads to undesirable current surges in the inverter's power circuits and the load at times transition from one control subrange to another,

The purpose of the invention is to improve the spectral composition of the output voltage of the converter in the process of the associated control of the frequency and voltage value carried out in the range

g-fo p

output frequencies F0 -s-s1, 6

by smooth

shock-free transition from one control subrange to another.

The goal is achieved by the fact that according to the proposed method in which the main valves of different phases of the converter are periodically turned on and off with a mutual phase shift of 60 e. hail., with for each valve during one half period from 0 to 180 el.grad. create a conduction zone, during the other half-period from 180 to 360 el. grades, create a closed state zone, within the clock interval of each conduction band from 60 to 120 el.grad and within the clock interval of each closed state zone from 240 to 300 el. hail. respectively, turn off and turn on valves (control signals) are formed, the number of which decreases sequentially with increasing output frequency of converter F, and at the initial output frequency F0 the clock intervals are divided into an even number of subintervals of equal duration, in the rightmost part of each of which specified signals

control, in the frequency range F0 - -to Fo in

centers of clock intervals form additional control signals with the corresponding control zone with a duration equal to

the duration of the clock sub-0.8

Fishing is defined as at each polo.

five

0

five

0

five

0

five

0

five

6F0n

the fault of the clock interval, the beginning of each first and the end of each last clock sub-interval is synchronized respectively with the beginning of the clock interval, with the boundaries of the specified additional control signal and with the end of the clock

interval, in the frequency range F0 - g-F0 within each half of the clock interval, the formation of each 1st, counting from the right marked synchronization points, the control signal (each (AND) th control signal, counting from the left marked synchronization points) is performed at change the output frequency of the converter from F0 to FI. F0n (l-1)

moreover, when changing «FI

2 (21-3) (1-1) + 1 in the output frequency from F0 to

FQ p (- 1) 2 (2l-1) (i-1j-1 inside each

clock subinterval form a control signal with a duration

(() nature | p FI inside, in the rightmost part of (I) -p right and (i-2) -n left from the middle of the marked halves of the clock interval of the clock subintervals, synthesize the control signals of the duration

,, 0.8 (21-3). .

l - d with / I 1 in the extreme right part

D Go P I I j

the segments located between the specified subintervals form control signals with a duration of (21-3) P-1) + 11v

FO P F0 P

frequency range in the extreme

the right parts of the marked halves of each clock interval generate one control signal with a duration

1 - J.6 FF 6For,

Figure 1 shows the structure of the main circuits of a three-phase single-bridge converter made on lockable thyristors; Fig. 2 shows timing diagrams illustrating an algorithm for generating control signals in accordance with the proposed method; FIGS. 3 and 4 are a functional diagram of a converter control system that implements the developed algorithm, as well as time diagrams of its operation.

I The timing diagrams presented in Fig. 2 and including the Uy cyclograms of the control zones of the valve A and the half-wave curves of the linear output voltage of the inverter UAB illustrate the control variant for p-8, at which the initial output frequency FO (fig.2a) sixties tigradusny clock intervals from 60 to 120 el.grad. in the conduction zone of the valves and from 240 to 300 el.grad. in the closed state zone, respectively, are divided into eight subintervals, shown in Figure 2 by arcs,

duration - el.grad. each

P.

(i.e., respectively, in b el.grad.). At the same time, in the central part of each clock interval, on an area of 12 el. additional control signals, which are opposite to the corresponding control zone, are generated, in particular, the switching pulses in the closed state zone. Within the first half of the clock interval, the beginning of the first sub-slot and the end of the last sub-slot are synchronized, respectively, with the start of the clock interval and the left border of the specified additional control signal. On the second half of each clock interval, the beginning of the first sub-interval is synchronized with the right border of the control signal, and the end of the last sub-interval with the end of the clock interval. In the extreme right part of each of these subintervals, the on and off valves of the control signals are formed, by varying the duration of which the output voltage of the inverter is controlled. The instants of the formation of the blocking valves of the pulses in Fig. 2 correspond to the zero level of the signals Uy, and the conductive state of the valves corresponds to a positive value of the signals. Similar to the formation of locking signals at intervals of 60-120 al. on the clock interval of 240-300 eh.grad. A synthesis of control valve turn-ons is carried out.

The total range of the associated control of the magnitude and frequency of the output voltage of the converter with the considered unbalanced control algorithm is FO - Tg - At c - FQ P

In this case, in the frequency range F0, the frequency is controlled by the constant smooth variation of the durations

the pauses between the main control signals and the control signals themselves in the areas close to the middle of the indicated half of the clock intervals. The regulation process takes place in two stages, carried out by two main reference algorithms; the boundary values of frequencies, which are transitional from one control range to another, are determined by FonTl-1V

2 (2i-3) (i-1) -M

Fo n (1-11) c. il and Fi

//

as

IR |

F ;:

2 (2i-1) (i-1) 1

 for odd m and i y

one

for even t, where m is the number of generated basic control signals within each half of the clock intervals.

On the control subbands, at which Fi F Fj + 1, control signals with a duration of

A 12 (2p-1) m-t) frequency change (duration of the clock interval) is produced at the expense of changing the duration of the indicated linear intervals of the output voltage curve corresponding to the interval 60-120 el.rad. the pauses between the main control signals, shown in Figure 2 by the arrows on the top. Their duration at the time the output frequency of the FI value converter reaches is reduced to zero. ,

In the frequency bands FI F FI, inside (M) -n right and (l-2) -n left from the centers of the half of the clock intervals of the clock subintervals indicated above, main control signals are formed with a constant duration defined by 0.8 (21-3) 12F0n (i -one)

In the extreme right part of the interval, located between the specified sub-intervals, a control signal of adjustable duration is generated ,, 0.8 g 1 2C2I-3

I -VTi - F

by changing which on the given subbands the output frequency of the converter is adjusted. A decrease in the value of e to zero is observed at frequencies f i. In the sub-range of the increased weekend hours "from U, - U..

that converter F0 y - F0 y in the extreme

the right side of each of the marked polokak

I iM / iri i ate onuu i

-3} (i-n + 1, (1-1)

wines of clock intervals form one basic control signal with proj 0.8, 1 1 A-T2- (tg-F57

by duty

)

on the upper frequency f ° n

when inside the clock inter2 1.6 shafts in their centers, they form one control signal with the duration

; - 1 - J.6 6F0n

Formation over the most part of the frequency range of operation of a three-phase FO - “- 0-8 Fmax B centers

clock intervals of additional control signals with a duration of 12 al. allows to completely exclude the most undesirable fifth harmonic component from the output voltage spectrum. Throughout the entire working range, the transition from one adjustment range to another is accomplished in an unstressed way by smoothly and gradually changing the duration of the control signals and the pauses between them.

In accordance with the described algorithm, in the time diagram of FIG. 2, illustrating the mode of conducting the control method, the absolute length of the control signals generated inside the subintervals shown by the upper arcs is constant, and the duration of the signals synthesized inside the subintervals designated by the lower arcs varies in the process of frequency control. In the analyzed control variant on the first sub-band, the frequency increase from the initial value equal to FO is produced by sequentially reducing the duration of the control signals generated inside the upper arcs of the clock subintervals indicated in Fig. 2a, taking into account the fact that i 3 depends on

1 - ° -8 (1 13 l -T2 (G TBT)).

The duration of the remaining main control signals at the same time remains constant and equal

one

I on g The noted process continues until the output frequency of the transducer reaches the value of P3.

1 TO

 - Fo, in which I decreases to zero (fig. 2b).

In the next adjustment interval, the frequency increase is accomplished by successively decreasing the duration shown in FIG. 26,

5 arrows left from the middle of the half of the intervals of the switching signals (pauses between the main control signals), the duration of the main signals themselves, taking into account the fact that i 2, varies

10 while depending on:

0811

I -tpg- (-pl p) up to the frequency Fa

The change of the output frequency from F2 to F2l Q-Fo is made, as shown in Fig. 2g, by changing the duration of the signal I -fa (-p and p) under the condition

i /

one

duration

signals

T20rV.,

Starting with the frequency Fa (figd) and up to the frequency F at FO 4 FO (fig.2e) inside each

a clock interval is formed by two main (not counting the central additional) control signal with a length of 0.8 t 1 1 h p

I-tg- (-pl-p) after

achieve the specified frequency -5- F0 4F0,

which corresponds to a value of 0.8 Fmax and

5 characterizes the transition point from asymmetrical to symmetric control mode (in the output half-wave, only three output pulses are formed instead of four), further regulation is carried out by varying (decreasing) the duration of central signals on the clock intervals according to

L- 1-J.6 1 0.2

5 l

The control unit (Fig. 3), which implements the proposed method of generating control signals as applied to the variant, functions as follows.

The output signal Ui of the frequency setting unit 1 is fed to the input of the generator 2 clock pulses forming a sequence of pulses, the following frequency

5 of which over the entire control range is 12 times the output frequency of the inverter. These signals are fed to the input of the generator 3 linearly varying voltage, synchronizing its operation,

whereby, as shown in FIG. 4, the output voltage of the generator 3 is symmetrical in both directions, the voltage Us is six times the output signal of the frequency converter, whose amplitude decreases in proportion to the output frequency, and is continuously detected by the amplitude sensor 4. From the output of sensor A, a signal proportional to the amplitude of the voltage Us is supplied through amplifiers 5 and 6 to the inputs of comparators 7 and 8, in which they are associated respectively with the output voltages of the generator 3 and Ug of the integrator 9, the storage element 10 of which is shunted by a key 11, controllable output signal of the comparator 7.

The transfer factors of amplifiers 5 and 6 are respectively 0.8 and 0.4. The output node of the integrator 9 includes a threshold node 12, which fixes the minimum (zero) voltage Ug, which through the OR 13 element is connected to the input of the counting trigger 14 connected to the switch 15 of the polarity of the integrator 9. the time period when the value of the signal Us exceeds the voltage level at the output of the amplifier 5, the comparator 7 issues a command to close the key 11, which shunts the accumulative element 10 of the integrator 9. Due to the connection diagram of the nodes 5-15 at the output of the integrato 9 and as shown in Figure 4, is formed symmetrical sawtooth voltage Ug voltage zero crossings with pauses at central portions of clock periods.

This signal Ug, being the main sweep voltage in the system, is fed to the inputs of the comparator nodes 16-18, the outputs of which include circuits for the formation of short single-pole pulses consisting, as shown with reference to node 18, of the logical inverter 19 and differentiating chains 19 and 20. The other inputs of the comparing nodes 16-18 receive signals from the outputs of adders 22 and 23 and amplifier 24 with a transfer ratio of 0.5, the inputs of which receive signals from the source 25 of the reference voltage and the integrator 26, At the moment of equality Commanded signals at the inputs of nodes 16-18 are synthesized by the system commands (short pulses) to form the fronts of the output pulses, which through the OR element 27 arrive at the input of the counting trigger 28, which is connected by its output to the information input of the logical distributor of control pulses on the converter valves 29 .

The output of the trigger 28 is also connected to the capacitor 30, which separates the constant component of the sequence of the pulse signals from the output of the trigger 28. The voltage of the capacitor 30 goes further to the divider 31, in which it is divided by the analog frequency reference signal Ui, as a result which, at the output of the divider 31, a voltage is formed at an appropriate scale proportional to the total duration of the output pulses over a half period. This signal goes further to the negative input of the integrator 26, which is connected to the second positive input with the source of the reference voltage 25, the amplitude of which is U25

0,8 imax,

where Usmax is the maximum amplitude of the generator 3 signal, is observed at the initial output frequency of the converter. Due to the above inclusion, the amplitude of the signal at the output of the integrator 26 is proportional to the value

(rI v1) is the duration of the main output pulses of the output voltage curve, and the signal at the output of summing amplifier 24 is proportional to the half duration of the main control signals.

In the process of coupled adjustment of the frequency and voltage of the converter, the internal feedback loop of the system, including nodes and blocks 26, 28, 30 and 31, provides for the control range from the initial frequency F0 to F21

 - | -2F0 continuous, implementable

according to the astatic principle, the formation of a correction signal arriving at the inputs of adders1 22 and 23 and directly to the comparator 18 and automatically maintaining the constancy of the total volt-second area of the output pulses over a half-period during the change of the output frequency. In this case, the implementation of the functional dependencies between the duration of the control signals, their temporary position and the current values of the output frequency of the converter, as well as the automatic transition from one control band to another, observed at the specified boundary frequencies Fr, are automatically implemented on this range. and fj.

Starting with the frequency Fa - | - value

U23 signal exceeds the sawtooth voltage amplitude Ug, by half a period

the linear output voltage curve is synthesized with four pulses of the same duration, the signal 1) 24 at the output of the amplifier 24 with a further increase in frequency decreases sequentially, reaching zero at the last cutoff frequency FI

 2 ° 3F0 0.8 Fmax. Half wave output

Converter signal after this point and up to the maximum frequency Fmax Fo n

1.6

- formed from three pulses on

half period. This moment is detected by a logical node consisting of a comparator 32, to one input of which a signal comes from the output of the amplitude sensor 4, and to the second a constant voltage is supplied from the first output of the source 33,

defined as khz (1)

n

By

signal of comparator 32 closes key 34 and switches key 35, after which comparing node 26 begins comparing the current value of the signal from with the voltage taken from the second output of source 33 and defined as iz (and) - and to the four-bit input register 37 is connected to the generator 2 clock pulse output.

Due to the above connection of the four-bit register 37 on the frequency range Fo-FI 0.8 Fmax, the required asymmetry of the control signal generation algorithm is provided. The numerically expressed states of the higher output bits Q / i, Qs, Q2 of register 37 in the output frequency period, as shown in Fig. 4, are respectively recorded as 100, 001, 000, 101, 110, 111, these signals are sent to clock inputs of the logic distributor 29 and determine by themselves the well-known algorithm for synthesizing control signals to the main gates of the three-phase inverter.

Thus, the proposed control method allows over most of the converter control range, in the Fo-0.8 Fmax zone, to ensure the complete absence of the most undesirable fifth harmonic component in the output voltage spectrum, and this is ensured in the simplest way, without additional switching of the valves power circuit, causing additional loss of electrical energy. The shape of the output voltage during the regulation process varies smoothly, thus eliminating the

ten

15

20

25

thirty

35

40

45

current in the power circuits of the inverter and the load, thereby improving the quality of the control process and the reliability of the operation of the converter systems as a whole.

Claims (1)

Claims The method of controlling a three-phase adjustable bridge converter, is that the main valves of different phases of the converter are periodically turned on and off with a mutual phase shift of 60 zl.grad. . form the conduction band, during the other half period from 180 to 360 el.grad. form a closed state zone, within the clock interval of each conduction band from 60 to 120 al. and a clock interval of each zone of a closed condition of gates from 240 to 300 el.grad. control signals with the corresponding control zone are formed, the number of which is successively reduced with increasing output frequency of converter F, and even number of subintervals of equal duration are formed at the initial output frequency FO within the clock intervals, at the end of each of which control signals are generated, characterized in that, in order to improve the harmonic composition of the output voltage of the converter in the process of the associated frequency control and s voltage emogo effected in output frequencies Fo FQ n -r-g- by smooth unstressed transition from one control band to another, in the frequency range Fo - j Fo in centers of clock intervals form additional control signals with the corresponding control zone with a duration equal to -off time duration jU subinterface 0.8 fishing is defined as 50 55 on each 6 F0n At the time of the clock interval, the beginning of each first and the end of each last clock subinterval is synchronized respectively with the beginning of the clock interval, with the boundaries of the specified additional control signal and with the end of the clock interval in the frequency range F0 -5- FO on each half of the clock interval of the formation of each i-ro, counting from the right synchronization points, control signal (of each (H) th control signal, calculated from the left-hand synchronization points) are performed when the output frequency of the converter changes from F0 to R x FQ P (I - 1) x 2 (2 1-3 AND I- 1) + 1 PREVIEW WHEN THE OUTPUT FREQUENCY CHANGE IS FROM F0 TO FI - F0n (l-1) - 2 (2 i - ПТТ- 1) - 1 INSIDE each clock subinterval, a control signal with duration Г 12 (° f-1) (4-l | n-) FI inside, in the extreme right part of (M) -n right and (i-2) -n left from the middle of the marked halves of the clock interval of the clock sub-intervals form signals Controlled 0.8 (2I-3) A 6F0n (i-1) in nor with duration the extreme right part of the segments located between the specified sub-intervals, generate control signals with the duration +1 jii ao / iwnvi / i v ii | / Wf-iwJi iv ri i s and o t r - 0.8 r 1 2 (2i-3Ki-1) 4 -T2 L FF0n (i-l) frequency range Fo n fo n in the extreme 0 five 0 32 The right parts of the marked halves of each clock interval form one control signal with a length of 0.8, 1 1 I am Fo n f. Fo n  hon ) and  "-1 - l Q in clock centers intervals form one control signal with duration 1-1 - 1.6 6Fo n } ь y P Fig.T gf 9 h i 09ash V "G A 4, M J / to7 | Fig.Z A