SU1720035A2 - Magnetic induction digital meter - Google Patents

Abstract

The invention relates to magnetic measurements and can be used for precision measurements in a wide range of induction of constant magnetic fields. The purpose of the invention is to improve the measurement accuracy. An element OR 7, an impulse generator 12, a counter 13, a decoder 14, a flip-flop 22 reversal, four flip-flops 23-26, six elements AND 16-21, a NOT 15 element, a second reversing counter 27 and a switch 11 are inserted into the meter. The meter also contains Hall sensor 1, switch 2, power source, synchronous detector-4, voltage converter - number of pulses 5, phase-sensitive element 6, reversible counter 8, binary-decryption decoder 9, digital indicator 10. Zil.

Description

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The invention relates to magnetic measurements, can be used for precision measurements in a wide range of induction of constant magnetic fields, and is additional to the main author. St. No. 367794.

The purpose of the invention is to improve the measurement accuracy.

FIG. 1 shows a functional diagram of a magnetic induction meter; in fig. 2 shows timing charts of the alternating output signal of the Hall sensor after the switch and after it is converted into a constant signal by a synchronous detector; in fig. 3 - timing charts of control signals.

The magnetic induction meter contains a Hall sensor 1, a switch 2, a power source 3, a synchronous detector 4, a voltage converter - the number of pulses 5, a phase-response element 6, an IL-I element 7, a reversible counter 8, a binary-decoding decoder 9, a digital indicator 10, switch 11, generator 12 pulses, counter 13, decoder 14, element 15, first, second, third, fourth, fifth, sixth elements AND 16-21, flip-flop 22, first, second, third, fourth triggers 23 -26, reversible counter 27.

The generator 12 pulses through the counter 13 is connected to the input of the decoder 14, the first output of which is connected to the first input of the first element AND 16, the second output to the first inputs of the second 17 and third 18 elements And, the third output to the first inputs of the fourth 19 and fifth elements And, the fourth output - to the control input of the binary-decoding decoder 9, the fifth output - to the installation inputs of the first 23

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and the second 24 flip-flops, the triggering input of the voltage converter - the number of pulses 5 and the set input of the reversing counter 27, the sixth output to the set inputs of the third 25 and fourth 26 triggers, the set input of the first reversing counter 8 and the first zero input of the reverse trigger 22, the seventh output to the control input of the switch 2, the second input of the first element AND 16 and the input of the element 15 are combined and connected to the output of the phase-sensitive element b, the first counting input of the reversing counter 27 is combined with the input Element OR 7 and connected to the output of the converter Voltage - the number of pulses 5, the output of which is connected to the first input of the sixth element And 21, the second inputs of the fourth 19 and fifth 20 elements And are connected to the output of the fourth trigger 26, the single input of which is connected to the first output reversible counter 27, the second output of which through the fifth element And 20 is connected to the second zero inputs of the third trigger 25 and the trigger 22 of the reverse, and its third zero input is connected to the output of the third element And 18, the output of the fourth element And 19 is connected single inputs of the second 24 and third 25 flip-flops and counting input of the flip-flop of the reverse 22, whose single input is connected to the output of the second element 17, the second, third and fourth inputs of which are respectively connected to the outputs of the first 23 and second 24 triggers and the element 15, the first output the third trigger 25, through the sixth element I 21 is connected to the second input of the element OR 7 and the second counting input of the reversible counter 27, and the second output to the second input of the reverse of the reversing counter 27, the single input of the first trigger 23 is connected to EYY RUNNING of the first element AND 16, the second input of the third element AND 18 is connected to the output of the reversible counter 8, the input of which is connected to the output of the element OR 7, the first input of the switch 11 is connected to the common bus, and its second input to the installation input of the counter 23, the output of the reverse trigger 22 is connected to the input of the reverse of the first reversible counter 8, the output of the trigger 26 is connected to the second inputs of the elements And 19, 20.

The device generates variable and unchanging control signals.

The variable control signals include the following signals.

but. The signal arriving at the control input of switch 2. According to this signal, in the first cycle of measurement the first pair

the opposite electrodes of the Hall sensor 1 through the switch 2 is connected to the synchronous detector 4, and the second pair of opposite electrodes of the sensor 1 through the switch 2 is connected to the power source 3. In the second cycle, the first pair of opposite electrodes of the Hall sensor 1 is connected via switch 2 to the power source 3, and the second pair of opposite electrodes of the sensor to the synchronous detector 4, With this connection:

Ui ± 1x + INE, U2 ± lx-UH3, 1X - Hall emf;

11ne - the voltage of nonequipotentiality;

b. Signal arriving at the trigger input of the converter. Voltage - number of pulses 5. This signal starts converting the analog input signal into a proportional number of pulses.

A signal arriving at the installation zero input of the reversible counter 8. With this signal, the reversible counter 8 is reset.

The signal input to the control input of the binary-decoding decoder 9. This signal is used to read the measurement result by the digital indicator 10 after the second measurement cycle.

e. To separate the signals of the first and second cycles and the signal generated after the end of the measurement process in both measurement cycles, the decoder 14 generates corresponding control signals at its first, second and third outputs.

The variable control signals include the following signals.

but. A signal arriving at the input of the reverse of the reversing counter 8 and reversing the counting direction in the reversing counter 8 depending on the changing operating conditions. In the first cycle at t Ixi 1 1), the non-reversible counter 8 always works on addition.

The direction of the counting in the reversible counter 8 in the second cycle depends on the following operating conditions:

- at I 1Х 1-1 ine1: 1 lxl lUH3l, + В or - В a control signal arrives at the input of the reverse of the reversible counter 8, which does not change the counting direction in the reversible counter 8. i.e. the reversible counter 8 in both cycles works on addition, where B is magnetic induction;

-with I Ix I IUH3 I, Their I IUi I and + B to the edge of the reversible counter 8 receives a control signal that changes the counting direction in the reversible counter 8, i.e. the reversible counter 8 in the first clock works on addition, and in the second cycle - to subtract;

-in them. MonG, I 1x1 Inei, and the input of the reverse of the reversible counter 8 receives a control signal that changes the count direction twice in the reversing counter 8, i.e. the reversible counter 8 in the first cycle works on addition, and in the second cycle the signal works on subtraction , and then - on addition;

- in case of I 1X1 Shne, the operation of the reversible counter 8 differs from its operation under the condition of 1X 9 Kne, in which case the operation of the reversing counter 8 changes during the first measurement cycle;

- when G 1x1 1 UHS and - B, the input of the reverse of the reversible counter 8 receives a control signal in which the reversible counter 8 in the first cycle first works on addition and then on subtraction; in the second cycle the reversible counter 8 changes its direction accounts, i.e., works on addition;

- when | 1X | "Sne and + to the input of the reverse of the reversible counter 8 receives such a control signal, in which the reversible counter 8 in the first cycle works on addition, in the second cycle the reversible counter 8 changes the counting direction twice ;.

- at 11x1 Shne, 1x m4, the polarity of the output signal of the phase-sensitive element in both measurement cycles is the same: (+, -) with - B and (-, -) with + B (Fig. 2g, c). With the same polarity of the output signal of the phase-sensitive element 6 in the second cycle, the counting direction in the reversible counter 8 does not change;

when I | x | 11ne. U the polarity of the output signals of the phase-sensitive element 6, regardless of the direction of the magnetic induction - B In both cycles will be (+, -) (Fig. 2e, k). When the polarity of the output signal is changed, phase-sensitive. the winding element 6 s - in the first cycle, the counting direction in the reversible counter 8 is changed in the second measurement cycle; ,

- under the condition Their I 1) ne, Their I У Unz, and - B, the counting direction is changed twice in the reversible counter 8 in the second measurement cycle.

First, in the second measure, he works on subtraction. When the number in the reversible counter becomes equal to zero, it starts working on addition.

b. The signal coming through the element OR 7 to the counting input of the reversible counter 8 (counting pulses).

These pulses, the number of which is proportional to the size of the dead zone, arrive at the reversible counter 8 when the output signal of the Hall sensor 1 is less than the dead zone of the phase-sensitive element 6.

Thus, from the cumulative result stored by the reversible counter 8, the value of the insensitivity zone of the phase-sensitive element 6 is excluded.

With Their I ine, - In the work is as follows.

In the first cycle, the reversible counter 8 works on addition.

If the output signal of the Hall sensor 1 is less than the dead zone of the phase-sensitive element 6, then the reversible counter 8 changes the counting direction, i.e. it works for subtraction.

The counting input of the reversible counter 8 through the element OR 7 receives counting pulses, the number of which is proportional to the output signal of the Hall sensor 1 in the first measurement cycle, which will be subtracted from the number stored in the reversible counter 8.

In the second cycle, the reversible counter 8 changes the counting direction, i.e., the reversible counter 8 in the second-cycle works on addition.

When I 1X I Shne, I + B work is as follows. In the first cycle, the reversive counter 8 works on addition.

In the second cycle, depending on the output signals of the phase-sensitive element b in both measurement cycles, the trigger 22 outputs a reverse counter 8 for reversing such a signal, which either changes the counting direction in the reverse counter 8 or the counting direction in the reverse counter 8 remains the same. In the first case, the reversible counter 8 works on subtraction, and in the second - on addition.

Since the output signal of the Hall sensor 1 is less than the value of the insensitivity zone of the phase-sensitive element 6, at the end of the second measurement cycle the trigger 22 outputs a signal for reversing the reversible counter 8, which changes the counting direction in the reversible counter 8.

The counting input of the reversible counter 8 through the element OR 7 receives counting pulses, the number of which is proportional to the output signal of the Hall sensor 1 in the second measurement cycle.

The operation of the proposed device occurs in two measurement cycles.

The initial setup signal coming from the fifth output of the decoder 14 to the zero state is set to a reversible counter 8. Triggers 22, 23.24 are set to the signal coming from the fifth output of the decoder 14 to the zero state.

The signal coming from the sixth output of the decoder 14 to the zero state establishes triggers 25, 26 and a reversible counter 27. From the output of the reverse trigger 22, the control signal of the reversible counter 8 is fed to the reversible counter 8, which reversible counter 8 works on addition.

In the first measurement cycle, the output of the Hall sensor 1 is U1 ± 1x + ine.

This value of the output signal of the Hall sensor 1 is due to the fact that the control signal at the first output of the decoder 14 connects the first pair of opposite electrodes of the Hall sensor 1 to the input of the synchronous detector 4, and the second pair of opposite electrodes of the Hall sensor 1 flows from the source 3 of power .

The output signal of the Hall sensor 1 Ui ± 1x + ine through the switch 2 and the synchronous detector 4 is fed to the converter. The voltage is the number of pulses 5.

The result of the conversion in the form of pulses is fed to the reversible counter 27, and through the element OR 7 to the reversible counter 8, counting in the forward direction:

 I 1x ± ine1,

where K is the voltage conversion factor of the voltage converter, is the number of pulses.

At the end of the first measurement cycle, the decoder 14 switches the switch 2. In the second measurement cycle, the output signal of the Hall sensor 1 will be U2 I ± Ix-Una I.

This voltage goes to converter 5, from where as a sequence of pulses goes to reversible counter 27, and through the element OR 7 to reversible counter 8. In reversible counter 8 depending on the ratio Their I and I UHS I Summing or subtracting the measurement results two

cycles. Information about the video operation in the second cycle is extracted using the phase-sensitive element 6. The flip-flop 22 of the reverse, depending on the state of the phase-sensitive element 6, in both measurement cycles gives a specific command signal to the reversible counter 8.

When I ix I I Une I, in the reversible counter 8 is summed

0 measurement results of two cycles, and when I Ix I I Una I - from subtraction.

Let Ui I -1x + INE 1,1) 2 I HX-INE I.

If the number N.1 in the first measurement cycle

less than the dead zone

5 phase-sensitive element 6, the trigger 26 does not work in the first cycle. Therefore, during the first measurement cycle, the input potential of the element 19 from the trigger 26 receives a positive potential allowing

0 passing the control signal of the third output of the decoder 14 through the circuit AND 19 to the single inputs of the flip-flops 24, 25 and the counting input of the flip-flop 22 of the reverse. Upon receipt of the control signal from the circuit

5 and 19, the trigger 24 outputs the inhibitory potential to an AND 17 circuit, and the trigger 22 changes its state. From the output of the flip-flop of the reverse 22, a signal is issued at which the reversible counter 8 starts working on the subtraction. In addition, the trigger 25. controlling the direction of the counting in the up-down counter 27 will be set to this state; wherein the reversible counter 27 works on subtraction.

5 At the same time the input pulses of the reversible counter 27 and the input of the reversible counter 8 through the element OR 7 and the element And 21 receive clock pulses of the converter Voltage - the number of pulses 5. When

0 the number in the reversible counter 27 will become zero, its output signal through the element 20 will set the trigger 22 to the zero state.

Thus, the flip-flop trigger 22 is placed in such a state that the reversible counter 8 works on addition.

The output signal of the trigger 25 prohibits the passage of clock pulses through

0 element And 21 to the inputs of the reversible counters 8 and 27. Therefore, at the end of the second measurement cycle, in the reversible counter 8, there is a measurement result of the second cycle, which at Ix I I 1) ne1 is equal to:

5 NЈ К I 1х-иНэ I -К | 1x-iNe1 + K I 1X + + and „e | KNK 1x + and„ e | Ix + unne.

The signals from elements 17 and 18 to the setup inputs of the trigger 22 are previously converted into narrow pulses by formers, which are not shown in the drawing, since they are used for their intended purpose.

If the output signal of the Hall sensor 1 UisHx + lWJ is greater than the dead zone of the phase-sensitive element 6 during the first measurement cycle, trigger 26 is activated and prevents the control signal at the third output of the decoder from passing through the circuit 19. At the same time, the direction does not change accounts in reversible counters 8 and 27, and the second input of the element OR 7 does not receive the clock pulses of the element 21, i.e., the reversible counter 8 will receive I Li-Unay I pulses.

In the second measurement cycle, when I bc Cne I, the measurement results of two cycles are summed, and at i bc I I 11ne, they are subtracted.

In the first case, the reversible counter 8 will record the number of pulses proportional to the Hall EMF:

N K | 1x-INEn-K11x + iu1 2k 1x1.

In the second case, when the number in the reverse counter 8 is equal to zero when the two clock measurement results are subtracted, the AND 18 circuit operates. It sets the trigger 22 to the zero state, at which the reverse counter 8 begins to work on addition.

As a result, the reversible counter 8 will record the number of pulses proportional to the EMF of the Hall:

 I Une-Nh I -K I ine-1x + 21x I C 111ne-1x I, 1-KI UHS-IX I + 2 I ine-1x -K I and „e-1x | + + 2k1x 2k x.

Let Ui I Чх + Une I. U2 I - x-UH31.

The output signal of the Hall sensor 1 through the switch 2 and the synchronous detector 4 is fed to the converter 5 voltage - the number of pulses. The result of the conversion in the form of a sequence of pulses through the OR circuit 7 is fed to the reversible counter 8, where it is stored:

NtHC I Ix + Una.

If the number N2 in the second measurement cycle is less than the magnitude of the dead zone of the phase-sensitive element 6, then the trigger 26 does not work.

Therefore, during the second measurement cycle, a positive potential is fed to the input of element 19 from trigger 26, allowing the control signal from the third output of decoder 14 to pass through element 19 of 19 to single inputs of trigger 24, 25 and the counting input of reverse trigger 22.

When the control signal of the element And 19 arrives, the trigger 24 outputs the inhibitory potential to the element And 17, and the trigger of operation 22 changes its state. In addition, the trigger 25 is set to such a state that the reversible counter 27 starts working on the subtraction. In this case, the input of the reversible counter 27 and the input of the reversible counter 8 through the element OR 7 are fed through the element And 21 clock pulses.

When the number in the reversible counter 27 becomes equal to zero, its output signal through AND 20 sets the trigger 22 and the trigger 25 to the zero state.

The output signal of the trigger 25 prohibits the passage of clock pulses through the element 21 to the inputs of the reversing counters 22 and 8.

Therefore, at the end of the second measurement cycle in the reversible counter 8 is

the measurement result of the first clock cycle, which with llxl l-lta is: M5g K | 1x + ine1 + K11x-ine-K | x-ine1 K | 1x + in1 +.

If the number of N2 in the second measure

is larger than the dead zone of the phase-sensitive element b, trigger 26 is activated and prohibits the passage of the control signal from the output of the third 26 decoder 14 through the element

And 19.

In this case, during the second clock cycle, the counting direction in the reversible counter 8 and 27 does not change, and the clock input does not arrive at the second input of the element OR 7.

pulses from the elements And 21, i.e., the reversible counter 8 will receive pulses: I lx-UH3 I.

As a result, in the reversible counter 8 there is a total result of two cycles, proportional to the Hall EMF:

with, N - K x + UH3i + K lx-UH3l 2Klx, with .. KPx + Inz-K | Ne-1x1 2K1x, the resultant measurement is decrypted by Binary Decoder 9 and read by a digital indicator 10. Phromula a and z obreten and Digital magnetic induction meter according to ed. St. No. 367794, characterized in that, in order to increase

accuracy of measurement, an OR element, a pulse generator, a counter, a decoder, a reverse trigger, four triggers, six AND elements, an NOT element, a second reversible counter and a switch,

moreover, the pulse generator through the counter is connected to the input of the decoder, the first output of which is connected to the first input of the first element And, the second output to the first inputs of the second and third elements I.

the third output to the first inputs of the fourth and fifth elements, And, the fourth output to the control input of the binary-decoding decoder, the fifth output to the installation input of the first and second triggers, the starting input of the voltage converter — the number of pulses and the installation input of the second the reversible counter, the sixth output - to the setup inputs of the third and fourth triggers, the set input of the first reversible counter and the first zero input of the reverse trigger, the seventh output - to the control input of the switch, the second the stroke of the first element AND and the input of the element EE are combined and connected to the output of the phase-sensitive element, the first counting input of the second reversible counter is combined with the input of the OR element and connected to the output of the voltage converter — the number of pulses, the second output of which is connected to the first input of the sixth And, the second inputs of the fourth and fifth elements And connected to the output of the first trigger, a single input of which is connected to the first output of the second reversible counter, the second output of which through the fifth element And the connection en with the second zero inputs of the second

trigger and flip-flop trigger, the third output of the fourth element whose non-zero input is connected to the output of the third element I, is connected to the single inputs of the second and third flip-flops and the counting input of the reverse trigger, the single input of which is connected to the output of the second element I, second, third and fourth inputs of which respectively connected to the outputs of the third and fourth triggers and the element NOT, the first output of the second trigger through the sixth element AND is connected to the second input of the OR element and the second counting input of the second rever The second counter is connected to the output of the first element AND, in addition, the second input of the third element AND is connected to the output of the first reversible counter, the input of which is connected to the output of the element OR, the first input the switch is connected to the common bus of the device, and its second input is to the installation input of the counter, the output of the reverse trigger is connected to the input of the reverse of the first reversible counter, and the output of the first trigger is connected to the second inputs of the fourth and n the scheme I.

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Claims (1)

Claim Digital meter of magnetic induction according to ed. St. No. 367794, characterized in that, in order to increase the measurement accuracy, an OR element, a pulse generator, counter, decoder, reverse trigger, four triggers, six AND elements, a second element, a second reversible counter and a switch are introduced into it, and the pulse generator through the counter is connected to the decoder input, the first output of which is connected to the first input of the first element And, the second output - to the first inputs of the second and third elements And, the third output - to the first inputs of the fourth and fifth elements And, the fourth output - to the control in it is a binary decimal decryptor, the fifth output - to the installation input of the first and second 5 triggers, the trigger input of the voltage converter - the number of pulses and the installation input of the second reverse counter, the sixth output - to the installation inputs of the third and fourth triggers, the installation input of the first reversible counter and the first zero input of the reverse trigger, the seventh output is to the control input of the switch, the second input of the first AND element and the input of the element are NOT combined and connected to the phase-sensitive output .element, the first counting input of the second reversible counter is combined with the input of the OR element and connected to the output of the voltage converter - the number of pulses, 20 the second output of which is connected to the first input of the sixth element And the second inputs of the fourth and fifth elements And are connected to the output of the first trigger, single the input of which is connected to the first output of the second reversible counter, the second output of which through the fifth element And is connected to the second zero inputs ^ of the second trigger and the reverse trigger, the third output of the fourth element nta The non-zero input of which is connected to the output of the third AND element, is connected to the single inputs of the second and third triggers and the counting input of the reverse trigger, the single input of which is connected to the output of the second And element, the second, third and fourth inputs of which are respectively connected to the outputs 10 of the third and fourth of the triggers and the element NOT, the first output of the second trigger through the sixth element AND is connected to the second input of the OR element and the second counting input of the second reversible counter, and the second output15 * * to the reverse input of the external counter, the single input of the fourth trigger is connected to the output of the first element And, in addition, the second input of the third element And is connected to the output of the first reversible counter, the input of which is connected to the output of the OR element, the first input of the switch is connected to the common bus of the device, and its second input - with the installation input of the counter, the output of the reverse trigger is connected to the reverse input of the first reversible counter, and the output of the first trigger is connected to the second inputs of the fourth and fifth circuits I. figure 1 I _M cos cat d) o'flxfiltol < wwwwvwwv Uj-tx + U / Sj n Uji ~ “(Jus. U '.. h + J j Z ^a ....... f _ΰ ^ _(χ -υ „, _ _Uh3 inc 3 * ,.,-in; TheirNo ^ s! e * υ ^ -ίχ -U _H3 -ίχ - y beats Jo Oz to ° Ι / ΤΜ7 ...............-...--, - 3¾] [ottoman "————- Fig.2