SU1713091A1 - Jk-flip-flip - Google Patents

Description

The invention relates to a pulse technique and can be used in the composition of an LSI system for collecting and processing information, as a functional element of sequential devices.

Known integral 1K-trigger containing 22 np-p and six multiemitger transistors, the device records information on the front of the clock pulse.

The drawback of the device is the large hardware costs required for the realization of the device, and low speed (

Lower hardware costs are required to implement a clocked 1K trigger containing 10 np and four multi-emitter transistors, the circuit contains a smaller number of inter-element links. The flip-flop is built using the state-dynamic principle. At the input of the RS flip-flop there are two controllable 1st K-signals and spacing elements.

The drawback of the device is the strict requirements imposed on the edges of the clock pulse. If rGf r (where r is the duration of the pulse generated at the output of the difference element), the control at the output of the difference element does not form and the circuit stops working. Therefore, it is necessary to additionally install a clock driver at the input of the trigger, since the standard maximum for TTL and TTL of the 3-series series is 1f (100--150) not, but in this case is unacceptable. The most close to the invention is the 1K-trigger, consisting of primary and

additional triggers, between the keys are the keys that allow on the clock signal overwriting information.

An additional trigger is an RS trigger. The main trigger contains 11 transistors and 10 resistors, the circuit has a fairly large number of interconnects.

The drawback of the device is the large hardware costs required to implement the main trigger.

The aim of the invention is to increase the reliability of the device and reduce its power consumption.

The goal is achieved by the fact that in I the K-trigger contains a main trigger, whose inputs are connected respectively to the forward and inverse outputs of an additional trigger, which contains six transistors and nine resistors, the first terminals of the first and second resistors are connected to the power supply bus, the base the first and second transistors, respectively, through the third and fourth resistors are connected to the common bus and their zmitters, and the collectors are connected respectively to the inverse and direct inputs of the additional trigger and to the first the pins of the fifth and sixth resistors, the second pins of which are connected to the first pins of the seventh and eighth resistors, the emitters of the third and fourth transistors are combined, the collector of the fifth transistor is connected to the first output of the ninth resistor, ten Schottky diodes are added, the second output of the ninth the resistor is connected to the forward output of the main trigger, the base of the sixth transistor is connected to the clock input, the collector is connected to the power bus, and the emitter is connected to the first output of the seventh resistor, the second output of which en with the base of the fifth transistor and through the tenth resistor - with its emitter and the base of the first transistor, the second terminal of the eighth resistor is connected to the base of the second transistor, the second terminals of the first and second resistors are connected respectively to the bases of the third and fourth transistors, KOTOpiJx collectors are connected to the cathodes of the first and second Schottky diodes, respectively, whose cathodes are connected respectively to the bases of the first and second transistors, the collector of the first transistor | ea is connected to the cathodes of the third and fourth diodes, ano The holes are connected to the bases of the second and third transistors, the collector of the second transistor is connected to the cathodes of the fifth and sixth Schottky diodes, the anodes of which are connected

the bases of the first and fourth transistors respectively, the base of the third transistor is connected to the anodes of the seventh and eighth Schottky diodes, the cathodes of which are connected respectively to the direct output of the main trigger and the K input, the base of the fourth transistor is connected to the anodes of the ninth and tenth Schottky diodes, cathodes which are connected respectively with the inverse output of the main trigger and the input.

The output function of the proposed device is as follows:. ,,,

Qt 1 - CQt-1 + GQt-1 KQt-1 - CQt-1 IQt-i, where (+), {-) are the arithmetic operations of summation and subtraction, respectively. In the C-0 storage mode, all transistors except the fourth and sixth (can be closed or open depending on the values of the input signals IQt-1 and KQt-i) are closed. When I K O and on the leading edge G of the pulse of the first and second transistors, which form a comparator trigger between them (comparison circuit), the device implements the Qt Qt-i storage mode; Qt-i is 0 or 1. By logical 1, we mean the preset input current level of the second transistor, And, and O, the input current level of the first transistor 12. The feedback information signal Qt-i will set the third current level 1h. And li l2, And l2 + 1h. Note that the current is controlled and appears only if Qt-i 1. Therefore, if the input capacitances of the first and second transistors are equal to (). the threshold voltages are identical (Unppi Unop2) then that trigger transistor will open faster, the base current (1b) of which is greater (torn Unop X

xCvc / 1b}. Successively6, in the storage mode on transistors and the trigger works as a comparator of input currents.

The drawing shows a schematic diagram of the 1K-trigger.

1K Trigger contains main and additional triggers, with the additional trigger contains ten resistors, six P – P transistors, ten Schottky diodes, the main trigger.

The feedback signal from the forward output of the main trigger 1 through the ninth resistor 2 is connected to the collector of the fifth transistor, the clock input of the device is connected to the base of the sixth transistor 4, the emitter of which through the seventh resistor 5 is combined with the base of the transistor 3 and the first output of the tenth resistor 6, the second output of which is combined with the emitter of the transistor 3, the first output of the third resistor 7 .. and the anode of the first Schottky diode 8, the cathode of which is connected to the collector of the third transistor 9, the emitter of transistor 4 through the fifth resistor 10 It is connected with 5 inverse output of additional trigger, direct input of main trigger 1, cathodes of the third and fourth Schottky diodes 11 and 12 and collector of the first transistor 13, the base of transistor 9 is connected to 10 anode of the seventh Schottky diode 14, second terminal of the first resistor 15 and through the eighth Schottky diode 16 with the K-input of the device, the collector of the transistor 4 is connected to the power bus and the first terminals of the first 15 and second resistors 15 and 17, the second output of the latter through the tenth Schottky diode 18 is connected to the 1-input of the device, the base of the transistor 13 is connected Nene with anodes of Schottky diodes 8 and 19, the anode of diode 18 is connected 20 to the anode of sixth diode 20, the cathode of which is combined with the inverse input of the main trigger 1, the cathode of diode 19, the second output of the sixth resistor 21, the collector of the second transistor 22, the inverse output 25 of the device connected to the inverse output of the main trigger 1 and the cathode of the ninth Schottky diode 23, the anode of which V is connected to the anode of the diode 18, the anode of the diode 11 is connected to the base of the transistor 22 through 30. the second Schottky diode 24 to the collector of the fourth transistor 25, the second output of the eighth resistor 26 and the first terminal of the fourth resistor 27, the first terminals of resistors 21 and 26 are combined with the emitter 35 of transistor 4, the base of transistor 25 is connected to the anode of diode 23, the direct output of the main trigger is connected to the forward output of main trigger 1 and the cathode of diode 14, the second terminals of resistors 7 and 27 40 and the emitters of transistors 9,13,22 and 25 are combined with a common bus.

Consider how the various input currents of the transistors 13 and 22, which form the trigger comparator 45, are set (with KQt-1 IQt-1 O, the transistors 9 and 25 are closed). Moreover, it is necessary to obtain the inequalities li l2 or li la + 1h. These inequalities are provided by the selection of resistors. Resistors 26 and 27 set 50 a current ii, resistors 5 and 6 a current r and, finally, resistor 2 and transistor 3 provide a current 1h at a high logic level of the feedback signal {Qt-i T); if 01–0, then p.55

The device works as follows.

If C O, then the 1K flip-flop is in storage mode, since in this case the transistors 13 and 22 are closed, which is not affected

on the state of the main trigger. Moreover, a change in the signal levels at the I and K inputs leads to a change in the state of only transistors 9 and 25. Note that in the storage mode, the additional trigger does not consume power (apart from the minimum currents flowing through the resistors 15 and 17).

If C 1, then on the leading edge (the transition from O to 1), transistor 4 opens and the trigger starts to be set to the state defined by the input signals l5t-i and KQt-1. When I K 1 (counting mode), the transistors 9 and 25 are closed, so the transistors 13 and 22 on 11 are open to open with their inputs by currents. Suppose that Qt-1 1, then the input current of transistor 13 (12 + 1z) is greater than the input current of transistor 22. Therefore, transistor 13 opens more quickly and selects the input current of transistors 22 and 9 through its open collector. an additional trigger produces a high signal, and at the inverse output a low logic level, which does not lead to a change in the state of the main trigger. Upon completion of the transient process, trigger connections are formed not only between transistors 13 and 22, but also between transistors 9, 13 and 25, 22 (we have three flip-flops), which makes it impossible to change the state of the flip-flop when changing as input signals (I and K) and the feedback signal, i.e. the trigger is set at the leading edge of the clock pulse. At the end of the clock pulse (C), the transistor 4 is closed and, as a result, the transistors 13 and 22 are closed, which does not lead to a change in the state of the main trigger.

If with the arrival of the next clock pulse (C) KQt-i O, IQt-i 1 (even before the arrival of C 1, transistor 4 is closed, transistor 25 is saturated), then unlocking of transistor 4 drives the appearance of input currents of transistors 13 and 22. Since the transistor 25 is saturated, the input transistor 22 is selected through the collector of transistor 25, and as the transistor 9 is closed, the transistor 13 opens and through its collector and Schottky diodes 11 and 12 ensures the locking of the transistors 9 and 22. At the end of the transition process, the input signal levels change does not cause a change no trigger.

When KQt-1 1, IQt-1 O, the transistor 22 opens on the leading edge of the next clock pulse, which closes the transistors 13 and 25. At the output

the main trigger produces a low level signal.

Note that in the storage mode with a low level at the clock input, the additional current trigger does not consume. Therefore, with a clock duration of two, an additional trigger consumes two times less power than in the prototype circuit, as the duty cycle increases, the power dissipation decreases. The circuit has a 1.5 times faster response, since, unlike the prototype circuit, the additional trigger of this circuit has a switching time of 4 ts (in the prototype circuit, the additional trigger has Gta). In addition, the additional trigger circuit does not contain multi-emitter transistors (i.e., 4 multi-emitter transistors are excluded), which allows to reduce the area occupied by the chip. The number of interconnects is reduced by 1.5 times (38 in the proposed scheme, 51 in the prototype scheme).

Thus, the proposed device realizes the functions of a K-flip-flop with the lowest cost of equipment and power, occupies a smaller area on a chip, is not inferior to analogs in speed and does not impose non-standard requirements on the parameters (front duration) of the input signals.

Claims (1)

Formula of the invention. 1K-trigger containing the main trigger, the inputs of which are connected respectively to the forward and inverse outputs of the additional trigger, which contains six transistors and ten resistors, the first terminals of the first and second resistors are connected to the power bus, the base of the first and second transistors respectively, the third and fourth resistors are connected to the common bus and their emitters, and the collectors are connected to the inverse and direct inputs of the additional trigger and the first the pins of the fifth and sixth resistors, respectively, the second pins of which are connected to the first pins of the seventh and eighth resistors, the emitters of the third and the first transistors are combined, the collector of the fifth TpaH3VicTopa is connected to the first output of the ninth resistor, characterized in that, in order to increase reliability and reduce power consumption, ten Schottky diodes are inserted into it, the second output of the ninth resistor is connected to the direct output of the main trigger, the base of the sixth transistor is connected to the clock input, the collector is with the power bus, and the emitter is connected to the first output of the seventh resistor, the second output of which is connected to the base of the fifth transistor and through the tenth resistor to its emitter and base of the first transistor, The second terminal of the eighth resistor is connected to the base of the second transistor, the second terminals of the first and second resistors are connected respectively to the bases of the third and fourth transistors, the collectors of which are connected to the cathodes of the first and second Schottky diodes, respectively, the cathodes of which are connected respectively to the bases of the first and second transistors, the collector of the first transistor connected to the cathodes of the third and fourth diodes, the anodes of which are connected to the bases of the second and third transistors, respectively; the collector of the second transistor is connected to the cathodes of the fifth and sixth Schottky diodes, the anodes of which are connected to the bases of the first and fourth transistors, and the bases of the third transistor are connected to the anodes of the seventh and eighth Schottky diodes whose cathodes connected to the direct output of the main trigger and the K input, respectively; the base of the fourth transistor is connected to the anodes of the ninth and tenth Schottky diodes, the cathodes of which are connected respectively to the inverse output of the main trigger and the f input.