SU1709240A1 - Method of measuring loop q-factor frequency detuning and device for - Google Patents

Abstract

The invention relates to a measuring and control technology and can be used to measure the parameters of semiconductor devices. The purpose of the invention is to increase the speed and accuracy of measurements by measuring signals at resonance at three fixed frequencies, with recording voltage levels at these frequencies. Then, the three values of the frequency and the corresponding values of the voltages on the circuit determine the value of the quality factor, and the voltage levels on the circuit are measured at arbitrary frequencies, the extreme values of which are located to the right and left of the resonant frequency. 2 Il.

Description

one

h

Let ft, fz, fa be the measurement frequencies that differ slightly from each other, and fi fa fa. In this case, fs is the frequency of measurement, which is different from the resonance (). The values corresponding to these frequencies are the resonant curve of the symbols yi, y2, knots. Exodus mzh (1) can be recorded;

U1.

PP

° (lF-tT Yt4 ..-- Iy fo fa / and Y1 / Y2 A, f2 / fi K are constant values of Then. Q pbli-V g fl. T 1 fofi I Q2 fo (- 1) + K fo f 1 (A - 1) (1 () -. 0 Taking into account that you decide on the ratio of fo with respect to t ≈ 2Q meters, we obtain (A2-1) ± A (K - f, 2 ° fl., j. Analyzing (5), you can still sign indicates that the points yi m y2 on different branches x of the resonant cree .... If to ensure the condition (6), with goes: Then ms (2) follows: 2ffbf | 1 -f Q Resh (9) from Q, we get;

Q VZI

(10) I

B (M - 2) -1 2 - N

f1, ri

(eleven)

f

f5

N - +,

(12) fi f5 fo is determined by no (7). Thus, the counts yi, y2, and nodes ila of fixed frequencies ft. h, h, therefore, it is possible to determine the true value of the goodness of the contour by (10). At the same time, the contour must be tuned and the resonance at the frequency fa is not particularly accurate, which reduces the requirement of the appr-ature that adjusts the contour. An example of the implementation of the method. A circuit containing inductance, warp-tuning, and measuring and varicap, connected to the discrete frequency generator h, 2, b- The tuning varicap connected to the bias source can change the capacitance of the circuit. The output signal of the circuit, the inputs to the amplifiers and the detector, is recorded by a measuring instrument (for example, a digital voltmeter). At the frequency of M3Mepet Hfl Tz, with the help of the varicap tuning g-s the circuit is tuned to resonance according to the maximum reading of the measuring device about which the ultrasound reading is taken. After that, the generator switches to the frequency fi and the sample is taken yi, then the frequencies ya are taken and the sample Y2 is taken From (3) and (4) the values A and K are determined, where K is a constant value, then by (7) the proper value is determined the resonant frequency of the fo circuit, which may differ slightly from the f3 frequency due to inaccurate tuning. Further, according to (11) and (12), the values of M and N are determined, and according to (8) - the value of B. The quality factor of the contour is determined by the dependence (10). The device contains a discrete frequency generator 1 high-frequency signal, amplifier 2, detector 3. threshold 4 and 5, the first three-input block 6 matches and the inverter 7, generators 8 and 9 clock pulses, the second three-input 10 and two-input 11 blocks of match, 12 and 13. digital-to-analog converters (D / A) 14 and 15. RS flip-flop 16. delay block 17, O-flip-flop 18. two-input blocks OR 19 and 20. three-input block OR 21, analog-to-digital converter (ADC) 22. distributor 23 pulses, block 24 interfaces, block 25 calculations and control, block 26 ind katsii capacitor 27 connection, a measuring circuit 28, consisting of inductor 29, capacitor 30 and a varicap 31 settings. Microcomputer Electronics 60 is used as the computing and control unit. Interface unit 24 is an I2 parallel exchange device. The input of the measuring circuit 28 is connected to the output of a digital-to-analog converter 15 and through a capacitor 27 to the generator t, and the output to terminal 32 for connecting the varicap 31 and through the series-connected amplifier 2 and detector 3d information input of the ADC 22 and the inputs of the threshold elements 4 and 5. Computing and control unit 25 is connected via interface block 24 to information and clock outputs of the A / D converter 22, display unit 26, with a distributor 23 pulses, the R input of which is connected to the Start bus, the first clock output to the first input of the IL block And 19, the second output - with the second input of the block OR 19. with the first input of the block OR 21, the output of which is connected to the control input of the ADC 22. the third output - with the first input of the block OR 20, the fourth output - with the second input of this block and with the second input of the OR block 21, the third input of which is connected to the R input of the RS flip-flop 16 and the output of the co-incident unit 6, the first input of which is connected to the output of the threshold element 4, to the second input of which the reference voltage U is fed, the second input of the threshold element 5 connected to the output of the digital-to-analog converter 14, and the output from the first the input of the block to match and through the inverter 7 with the second input of block 6 of coincidence and the R input of D-flip-flop 18, the output of which is connected to the second input of block 10 of coincidence, the logical level 1, C-9KHOD and third input are fed to the D input the coincidence unit 6 is connected to the output of the delay unit 17, the input of which is connected to the counter bypass 13, the R input of which is connected to the Start bus, the information output is connected to the input of the D / A converter 15, and the output of the coincidence unit 11 whose first input is connected to the generator 9, the second input - with the output of the RS-flip-flop 16, the S-input of which is connected to the Bus The third input of the coincidence unit 10 is connected to the output of the generator 8. And the output is connected to the counter 12, the R input of which is connected to the Start bus, and the information output of the input of the DAC 14 whose output is connected to the second input of the threshold element 5. One terminal for the varicap connection is connected to the output of the measuring circuit 2R, and the other terminal is connected to the common bus. The device that implements the method works as follows. In the initial state, generator 1 produces a sinusoidal frequency voltage at which the quality factor of the circuit is measured. The varicap under test is connected to terminals 32, after which a Start impulse is formed, with the arrival of which the counters 12 and 13 are twisted. The impulse distributor 23 is set to a state. in which there are no signals at its outputs, RS-flip-flop 16 is set to 1, which gives permission for the passage of clock pulses from generator 9 to counter 13, a voltage is generated at the output of DAC 15, which controls the capacitance of the varicap. The input clock pulse of the counter 13 through the delay block 17, the delay time of which is determined by the time of establishing transient processes in the circuit: counter 13, DAC 15, circuit 28. amplifier 2, detector 3. threshold element 5, sets the C-input to one D-flip-flop 18, to the D-input of which logic level 1 is applied. At the same time, if as a result of a change in capacitance of the wrench, the output voltage of the detector 3 exceeded the voltage level at the output of the DAC 14, at the output of the threshold element 5 the logical level Ii which one by one with The trigger 18 is triggered by clock pulses from the generator 8 through the block 10 to match 12. The increase in the code in the counter 12 occurs until then. until the voltage at the output of the DAC 14 exceeds the signal level of the detector 3. In this case, the output is poro-. the logical element O will appear at the left of the element 5. The pulses to the input of the counter 12 will stop. At the output of the inverter 7, the logic level G will arise, which will set the trigger 18 to the zero state. If by the moment of arrival of the pulse to the C input of the trigger 18, the threshold element 5 was in the zero state (the voltage at the output of the DAC 14 exceeded the voltage of the detector 3), the output of the inverter 7 will be the logic level 1, the holding trigger 18 in the zero state nii, i.e. if the variation of the varicap capacitance does not occur (the capacitance is far from the resonance), the trigger 18 does not turn on, at the output of the detector and the DAC 14 the voltage is zero. In this mode, the circuit is about; as long as the output voltage of the detector does not increase the voltage, the value of the monitor will monitor the DAC 14. When the voltage of the detector exceeds the reference level U. At the output of the threshold element 4, a logical state of 1. arrives bp In this case, if the signal at the detector output increases when the output voltage of the DAC 15 changes, the logic level of 1 m will be monitored at the output of the threshold element 5, this level will occur at the output of the inverter 7 during the melpulse output of the delay block 17 0 and the signal at the output of block 6 does not form a match. This happens until then. while the signal at the detector output when counter code 13 is changed, grows. If, as a result of changing the code of the specified counter, the signal at the detector output decreases (the varicap capacitance becomes less resonant), but the inverter output 7 is in the logical state T, the pulse from the output of the delay block 17, passed through block 6 coincides, sets to zero the trigger 16, the clock pulse from the generator 9 s, the counter 13 stops, the loop 28 is tuned to resonance. At the same time, the ADC 22 is started with the same pulse. A code proportional to the resonant signal at the output of the detector 3 is triggered. Upon completion of the formation of the code, the ADC 22 generates a signal End of Conversions that cocks one meteor 24 of the conjugation block. The ADC code is read and transmitted in the calculation and control unit. At the end of the readout, the computational control byyok generates a pulse on one mz of the registers of the state of the interface block 24, which is not a clock output of the distributor 23 pulses, after which the distributors 23 come to the rtepsoM output, which translates through bpoc OR 19 oscillator 1 at frequency fi; the second clock pulse of distributor 23 is generated by software with the delay necessary to establish transitional oscillations arising as a result of the frequency pattern. According to the second state, the distribution unit 23 via the block OR 21 is started by the ADC and its code access to the calculation and control block). Similarly to the described, switching to the frequency f2 occurs and the third ADC code is sent to the control unit of the manipulation, after which (7) the true resonance frequency fo is calculated {since the frequency C due to the discreteness of the DAC 14 and the final sensitivity of the threshold device B will be several higher than fo) and from (10) the true value of the quality factor of the circuit with the varicap is calculated, which through the output register of the conjugation unit 24 enters the display unit 26. The method can be used to deflect varicaps by Q in the mode of fixed capacitance, since the resulting Q of the circuit with a waps / KanoM boundary level with postokine eMKocTs is a constant value. The method has a higher accuracy of the performance. as well as relative simplicity in practical reai saiiMM, because it contains, by osnoanom, devices implemented commercially by the industry, Formula GO1. The method of measuring the Q-factor of the congur by detuning the frequency, which means that the circuit is tuned and the resonance at the frequency is measured by measuring capacitance the settings m calculate the voltage levels on the circuit at the moment of resonance, after which the levels of the voltage on the circuit are measured from the top and bottom of the resonant circuit, and three values are measured pilots at sootvetstvuyuschg m and voltage readings on the contour determined yelichiiu Q, characterized in that. for the purpose of increase of speeds and ACCURACY of measurements. the voltage levels on the circuit measure gfi arbitrary frequencies, the extreme values of which are located to the left of the right of the resonant one, while the quality factor of the circuit is determined from the maximum value of V (M - 2) 4-2 Where "V) ± y, () 8 knots VI , 1. 3 - let's equalize the circuits on the circuit, remove COOTzatst; / - t at frequencies fi, f2. fs. npvt 3TOf fi f, - f:.; 1 - Measurement frequency, am / 1ch8 from resonant resonance fo. 2 A device for sound quality KOHTVPS and a frequency detuning method, containing an emissive circuit, a discrete frequency generator, frequency indices, as well as S TQSb, fTO. from the chain to increase the speed

and measurement accuracy, a calculation and control unit, an interface unit, a pulse distributor, an analog-to-digital converter, two two-input OR blocks, a three-input OR block, RS trigger, two clock pulses are entered into it. two-input and three-input bi-match, two counters, two digital-to-analog converters, delay unit, D-flip-flop. coupling capacitor, amplifier, detector, two threshold elements, inverter, second three-input matching unit. at that, the computing and control unit is connected via the interface unit with the information and clock outputs of the analog-digital converter, with the display unit, with the pulse distributor, whose R-BXOA is connected to the Start bus, the first clock output with the first input of the first two-input block OR, the second output is with the upstream input of this block and the first input of the three-input OR block, the output of which is connected to the control input of the analog-digital converter, the third output - to the first input of the second two-input block OR, the fourth out one - with the second input of this block and with the second acode of the three-input OR block, the third input of which is connected to the R input RS-trigger with the output of the first three input matching block, the first input of which is connected to the output of the first threshold element, one input of which is connected to the reference voltage terminal, the second input - with the detector output, the information input of the amalo-digital converter and the first input of the second threshold element, the input of which is connected to the output of the first D / A converter the secondary input of the second three-input match block and via the inverter with the second input of the first three-input match block and the 5 R input of the D-flip-flop, the output of which is connected to the second input of the second match block, the D input and the third the input of the first three-input coincidence block is connected to the output of the block, the delay, the input of which is connected to the input of the first counter, the R input of which is connected to the Start bus, the information output to the input of the second digital-analog converter and the output of the two-input converter coincidence lock, the first input of which is connected to the first clock generator, and the second input - to the output of the RS flip-flop, the S input of which is connected to the Start bus, the third input of the second

0 of the three-input coincidence unit is connected to the output of the second clock generator, and the output is connected to the second counter, the I-input of which is connected to the Start bus, and the information output is connected to the input of the first

5 digital-to-analog converter, the detector input through an amplifier is connected to the output of the measuring circuit, with terminals for connecting the varicaps, and the measuring circuit consists of inductance

0 and the varicap tuning, the input of which is connected to the output of the Second Digital-to-Analog Converter and, through a coupling capacitor, to the output of a discrete frequency generator of a high-frequency signal, control,

The 5 inputs of which are connected to the outputs of the OR blocks, the first terminal for connecting the varicaps is connected to the output of the measuring circuit, the second terminal is connected to the common bus.

Claims (2)

Claim 1. A method of measuring the quality factor of a circuit by the frequency detuning method, which means that the circuit is tuned and the resonance is at the measurement frequency by changing the tuning capacitance and the voltage level of the circuit is counted at the moment of resonance, after which the voltage levels of the circuit are measured at frequencies above and below resonant, and then from three values of the frequency and the corresponding readings of the voltage on the circuit determine the value of the quality factor, I distinguish it with the fact that. in order to improve the speed and accuracy of measurements, the voltage levels on the circuit are measured at arbitrary frequencies, the extreme values of which are located to the left and to the right of the resonant, while the quality factor of the circuit is determined from the expression a ~ f r ^ in ² ~ .....—, 'In ² (M - 2) 4-2 - N where And, fl M yi, Y2, kn ~ voltage levels on the circuit, taken according to the test at frequencies fi. f2. fa. in this case fi <f ?, - fa: fa is the measurement frequency that is different © t of the resonant frequency f _o . 2. A device for controlling the quality factor of a circuit by the frequency detuning method, comprising a measuring circuit, a discrete frequency generator of a high frequency signal, an indication unit, characterized in that. what. in order to increase the speed and accuracy of measurements, a calculation and control unit, an interface unit, a pulse distributor, an analog-to-digital converter, two two-input OR blocks, a three-input OR block, an RS-flip-flop, two clock generators, two-input and three-input boky are introduced into it coincidence, two counters, two digital-to-analog converters, delay unit, D-flip-flop, coupling capacitor, amplifier, detector, two threshold elements, inverter, second three-input coincidence unit, while the calculation and control unit connected via the interface unit with the information and clock outputs of 15 analog-to-digital converters, with an indication unit, with a pulse distributor, whose R-input is connected to the Start bus, the first clock output is with the first input of the first two-input OR block, 20 the second output - with the second input of this block and with the first input of the three-input OR block, the output of which is connected to the control input of the analog-to-digital converter, the third output is with the first input 25 of the second two-input OR block, the fourth output is the second input of this block and with the second input of the three-input OR block, the third input of which is connected to the R-input of the RS-trigger and with the output of the first three-input 30 matching block, the first input of which is connected to the output of the first threshold element, one input of which is connected to the voltage reference terminal, the second the input is with the detector output, the information input of the analog-to-digital converter AND with the first input of the second threshold element, the second input of which is connected to the output of the first digital-to-analog converter, and the output is with the first input of the second three-in one block of coincidence and through an inverter with the second input of the first three-input block of coincidence and the R-input of the D-trigger, the output of which is connected to the second input of the second block of coincidence, the logic level, C-input and the third input of the first three-input block are fed to the D-input matches are connected to the output of the block, the delay, the input of which is connected to the input of the first counter, the R-input of which is connected to the Start bus, the information output is to the input of the second digital-to-analog converter and to the output of the two-input matching block, the first input which is connected to the first clock generator, and the second input to the RS-trigger output, the S-input of which is connected to the Start bus, the third input of the second three-input coincidence block is connected to the output of the second clock generator, and the output to the second counter. The R-input of which is connected to the Start bus, and the information output is to the input of the first digital-to-analog converter, the input of the detector through the amplifier is connected to the output of the measuring circuit, with terminals for connecting varicaps, the measuring circuit consisting of inductance and a tuning varicap, whose input is connected with the output of the Second digital-to-analog converter and through a coupling capacitor - with the output of the discrete frequency generator of a high-frequency signal, the control inputs of which are connected to the outputs of the OR blocks, the first the lemma for connecting the varicaps is connected to the output * of the measuring circuit, the second terminal to the common bus. X ’. Compiled by Π. Tarasenko