SU1707555A1 - Direct current voltage level indicator - Google Patents

Abstract

The invention relates to the field of electrical measurements and can be used to indicate the level of the voltage. direct current. The aim of the invention is to improve the stability of the device. The measured voltages through the scaling amplifier 1 are fed to the gate of the field-effect transistor 12, changing the resistance of its channel and the constant charging time of capacitor 1. The voltage converter 2 at the end of the trigger pulse produced by the frequency divider 8, pulse, the duration of which is proportional to the input voltage. During this pulse, the counter 3 counts the pulses of the generator 7 clock pulses about Decipher-. The ra- tor b converts the variable counter code 3 into a unitary code and alternately illuminates the display elements 5.1-5.N. The introduction of a frequency divider 8, a scaling amplifier 1, and the execution of a voltage converter 2 in a pulse duty cycle in the form of inverters 9 and 11, a diode 10, a capacitor, and a field-effect transistor 12 make it possible to reduce the dependence of the pulse duty factor on the influence of destabilizing factors. 2 il. c with FIG. T

Description

The invention relates to electrical measurements and can be used in devices for indicating the level of direct current voltage

The aim of the invention is to improve the stability of the device.

FIG. Figure 1 shows a functional electrical circuit diagram of a DC voltage level indicator; in fig. 2 - time diagrams for working devices.

The device contains a scale amplifier 1, the input of which is the input of the device, and the output is connected to the analog input of the voltage converter 2 to the pulse duty cycle, the output of which is connected to the reset input of the counter 3, the outputs of which are connected to the corresponding inputs of the decoder 4, the first terminals. The displays 5. are connected to the corresponding outputs of the decoder, except for the first, the second outputs of the display elements are connected to the power supply bus 6. The clock input of the counter 3 is connected to the output of the generator of 7 clock pulses, which through a frequency divider 8 is connected to the start input of the voltage converter 2 and the pulse width, which is the input of the inverter 9, connected to the anode of the diode 10, the cathode of which is connected to the output the inverter 11 and is the output of the voltage converter 2 to the pulse duty cycle, the analog input of which is the gate of the field-effect transistor 12, the source of which and the first terminal of the resistor 13 are connected to the common bus, and the drain and the second terminal of the resistor 1.3 , - with the input of the inverter 11, which through the capacitor 1A is connected to the output of the inverter 9.

The DC voltage level indicator operates as follows ,, i

Displayed voltage enters

through the scale amplifier 1 to the analog input of the voltage converter 2 to the pulse duty cycle, which is made in the form of a waiting one-oscillator with a variable duration of formation

mog pulse. Triggered pulses (FIG „2chz) arrive

An input of the inverter IOP 9, at the output of which a negative voltage drop appears, discharging the capacitor 1 through

0 0 5 0

five.

five

shield diodes CMOS inverter. to zero (Fig. 25). Upon completion of the trigger pulse at the output of the CMOS inverter 9, a positive potential is transmitted through a capacitor to the input of the CMOS inverter 11, the output of which is a logical O, which sets counter 3, to the zero state. Condensate capacitor C is charged by the current flowing through the resistor 13 and the open channel of the field-effect transistor 12. The resistance of the coil of the field-effect transistor 12 is determined by the voltage applied to its gate through the scaling amplifier 1 from the input of the device

Thus, the charge time of a capacitor depends on the level of the input voltage. As the capacitor 1 is charged, the voltage at the input of the CMOS inverter 11 goes over the response threshold, switching it to one state. At this moment (FIG. 2b), the counter 3 operates in a clock pulse counting mode, while its output code increases. The changing binary code of counter 3 is converted — decoder k into unitary

code (figv-d).

The alternating second, third and subsequent outputs of the decoder are alternately switched to the active zero state, illuminating elements 5.1–5.N alternately connected to the terminals

At the moment when the next trigger pulse arrives at the input of the inverter 9, the output voltage of the inverter 9 shows a negative voltage drop, which discharges the capacitor 1 through the CMOS protective diodes of the inverter 11 to zero (Lig.2b). At the end of the trigger pulse, the process repeats.

The counter 3 stops counting and is set to the zero state. When the code is zero, the output of counter 3, and therefore, at the input of the decoder k, its recourse output is set to the active zero state, to which none of the display elements is connected, the other outputs the transition t in the passive high. condition, what causes quenching

elements 5.1-5 indications I.

The repetition frequency of the trigger pulses from the output of the divider 8 is chosen longer than the eye recovery time, which provides observation of the 5.1–5oN elements of the light of the ruler, the length of which is proportional to the similar signal, the constant charging time of the capacitor 1, the frequency of the trigger pulses output divider 8, the initial, output voltage of scaling amplifier 1 is chosen so that in the absence of a signal at the input of amplifier 1 / the residual voltage on the capacitor b at the moment of arrival of the trigger pulse is slightly above the threshold of the inverter actuation 11 "However, no one element will not display svetits. With an increase in the input signal level, the constant of the charge time of the capacitor I t decreases, and the time of the voltage transition at the input of the inverter 11 through the operation threshold changes,. The resolution time of the counter 3 operation will also vary, which will lead to the ignition of 1,2,3 ... elements. Thus, the indicator line can be adjusted from the zero level of the input signal

Claims (1)

Formula of the invention A DC voltage level indicator containing a voltage to pulse ratio converter, N display elements, a clock generator, the output of which is connected to the clock input of the counter, the outputs of the meter are connected 5 0 5 0 five with the corresponding inputs of the decoder. torus, the second and subsequent outputs of which are connected to the first terminals of the corresponding indication elements, characterized in that, in order to increase stability, a frequency divider and a large-scale amplifier are introduced into it, and the voltage transducer to pulse ratio co. holds two KNOP inverters with input protection diodes, a capacitor, a diode, a field-effect transistor and a resistor, a field-effect transistor gate is connected to the analog input and the transducer is connected to the first inverter and the anode, the diode, whose cathode is connected to the output of the second inverter and the output of the voltage converter to the pulse duty cycle, the output of the first inverter is connected via a capacitor to the input of the second inverter, the drain of the field-effect transistor and the first output of the resistor, sec The output of which and the source of the field-effect transistor are connected to the common bus, the output of the clock generator: x pulses is connected to the start input via a frequency divider: - l voltage i-Mnyjucos, whose output is connected to the reset input of the counter, the device input through the large-scale the amplifier is connected to the analog input of the voltage converter in the pulse duty cycle, the second terminals of the display elements are connected to the power supply bus, Fie.2