SU1705800A1 - Pulse period-to-pulse duration meter - Google Patents

Abstract

The invention relates to a measurement technique and can be used in experimental physics, radar electronics. The aim of the invention is to increase the speed of measuring the duty ratio. The duty cycle meter contains a pulse and pause separation unit 1, charge unit 2, linear discharge trigger 4, charge-discharge unit 5, stable current source 6, voltage-current converter 7, comparator 9, element 10, generator 11 counting pulses, the first counter 12 pulses, a digital reading device 13. In the device entered the second counter 3 pulses and the second comparator 8. 2 Il.

Description

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about

The invention is washed to the measurement technique and can be used in experimental physics, television, electronics, oediolokatsiya.

The purpose of the invention is to increase the speed of measuring the duty ratio,

Figure 1 shows the block diagram of the duty cycle meter: figure 2 shows the timing diagrams explaining its operation.

The first exit of the pulse extraction unit 1 m-pause is the device input, the second is the start input, the first output is connected to the first inputs of the charging unit 2 and the second 3 pulses, and the second

- with the input of the installation of the trigger A of the linear discharge .-; The main input of the charging unit 5, the current of which is connected to the output of the stable current source and the second input of the charging unit 2, the third input through the voltage converter 1 is the current

- to the output of the charge unit 2 and the first input of the second comparator 8, the fourth input to the output of the second comparator 8 and the second input of the second with e) 3 pulses, and the output to the second in U. and l of the second comparator 8 and the input of the first comparator 9 The output of which is connected to the reset input of the trigger 4 of the linear discharge, the v / o of which is connected to the third g / ods o, o2 2 zergdz, the fifth input of the block z z.f dz-ra.chr and the first input of the element I 10 , the second input of which is connected to h. hn / -. eneparops i 1 counting pulses, r POs d. to the input of the first chick 12 im. r, -., which is associated with the first input of a Uv-1-hchnogo reading unit 13. The second course of which is connected with the output of the 3 pulse pulse counter.

The device of the gods is as follows .. OM.

In the initial state, the device output is blocked, o & and the capacitor of the charge-discharge unit 5. b jo-.l 2 bit discharged, tr-hg. the bit is in state O, the input of the element I 10 is closed.

By., 3. (Fig. 2a) allocation unit 1 and .fiv.-r ..- for sa / zy from the input trace. i and pulses (Fig.26) Forming signals on outcomes. : (figv), ppny for tepnog.ti impu ;; ss, t T - T, equal to the pause r / th pulse (Fig. 2d). During r, the source B of a stable gok is connected to a charge unit 2, where the stage of charging is carried out.

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hd h - charge current:

C r-cumulative condens-CriTOOr bls-a.

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The value of Ur is remembered at the time of the measurement and is converted by the converter 7 voltage - current to discharge current.

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where R3 is the equivalent resistance at which the conversion process takes place.

At the same time, the signal T records in the counter 3 pulses a unit duty cycle. During the signal t (Fig. 2d), a stable current source 6 is connected to a storage capacitor of the charge-discharge unit 5, the output of which is connected to the inputs of the comparators 8. 9. The voltage input Ur is supplied to the other input of the comparator 8 from the output of the charge unit 2 which is a reference. As a result, the comparator 8 compares the value of Ur with the linear accretion voltage at the output of charge-discharge unit 5 Ut. 8, the moment Ut Ur at its output (Fig. 2g) a logical pulse appears, which dumps the charge of the capacitor of the unit 5 to the initial state. At the same time, the second duty cycle is entered into the counter of 3 pulses. After resetting, the process of accumulating charge to Ur on the capacitor of charge-discharge unit 5 is repeated. At the output of the comparator 8, a logical pulse appears again, which adds 1 to the counter of 3 pulses and resets the charge of the capacitor to its initial state. The process will be repeated until the end of the signal t. Thus, the counter 3 pulses will register an integer r laid in the interval t. Taking into account the previously entered unit of information in the counter 3 pulses corresponds to the whole part of the duty cycle Q. B the instant of termination of the signal t, the voltage at the output Ui of block 5 will be less than the value of Ur, which transforms about the interval tp (Fig. 2e).

By decreasing the pause signal t, the trigger 4 of the linear discharge is set to 1, as a result, the voltage-current converter 7 is connected to the storage capacitor of the charge-discharge unit 5. From this point in time, the capacitor 5 is discharged by a current proportional to the voltage Ur to its initial value. The voltage of the output of block 5 is monitored by comparator 9. The signal from its output returns the trigger to its initial state. The discharge time xp (Fig. 2z), selected by the linear-discharge trigger 4, is converted into a digit using an AND element 10, a generator of 11 counting pulses, and a counter of 12 pulses. The number recorded by this counter represents the fractional part of the duty ratio Q (Figure 2e).

Claims (1)

The advantage of the proposed device in comparison with the prototype is to increase its speed. In the proposed device, after the first unit Q is entered into the counter (during a pause), the counting of whole porosity portions occurs and only the remainder of the integer portion is converted by an amplitude-time method into a digit. In the prototype, after entering the first unit, the stage of charging the capacitor of block 5 to the end of the pause t occurs. Then, the accumulated value Uto is converted by the amplitude-time method into a digit. Thus, the conversion time of the value Uto is longer than the conversion time of the residue Ui. DETAILED DESCRIPTION OF THE INVENTION A duty cycle meter comprising a pulse and pause separation unit, a stable current source, a charge-discharge unit, a charge unit, a voltage-current converter, a first comparator, element I, a counting pulse generator, a first counter and a digital reading device characterized in that, in order to increase speed, a second comparator and a second counter are entered into it, the first input of the pulse extraction and pause unit being the device input, the second input being started, the first output is connected to the first inputs s charge and the second block the counter, and the second output is with a linear discharge trigger installation input and the first input of the charge-discharge unit, the second input of which is connected to the output of the stable current source and the second input of the charging unit, the third input through the voltage-current converter to the output the charge unit and the first input of the second comparator, the fourth input to the output of the second comparator and the second input of the second counter, and the output to the second input of the second comparator and the input of the first comparator, the output of which is connected to the reset input of the linear discharge trigger, the output of which is connected to the third input of the charging unit, fifth the input of the charge-discharge unit and the first input of the element I, the second input of which is connected to the output of the counting pulse generator, and the output to the input of the first counter, the output of which is connected to the first input of the digital counting device, the second input of which is connected to the output of the second counter. / Ј1 well t - t-t Ј1 well