SU1699002A1 - Device for measuring and simulating electrical characteristics of digital channels - Google Patents

Abstract

The invention relates to telecommunications. The purpose of the invention is to reduce the measurement time and extend the functionality by measuring the jitter of the signal phase. In block 12, the received signal is compared with the signal from the output of sensor 10. When both signals are looped, the signal at the output of block 12 corresponds to an error in the received information. In block 11, ostacs or symbols are dropped in the information signal. 1 il.

Description

The invention relates to telecommunications and is intended to measure and simulate the electrical characteristics of digital channels in the process of tuning, testing and operating channels and communication equipment of digital transmission systems (DSP),

The purpose of the invention is to reduce the measurement time and enhance functionality by measuring the phase jitter of the signal.

The drawing shows a structural electrical diagram of a device for measuring and simulating the electrical characteristics of digital channels.

The device comprises a clock pulse generator 1, a signal phase jitter sensor 2, a test signal sensor 3, an input unit 4, an error generating unit 5, a slipping sensor 6, a signal delay unit 7, an output unit 6, block 9; jitter measurements Phases, sensor 10 reference signals, block 11 detect slippage, block 12 comparison, block 13 cyclic phasing. a clock synchronization unit 14, a signal passing time meter 15, a slipping counter 16, a display unit 17, an error counter 18, a measurement session duration counter, and an operation mode setting unit 20.

A device for measuring and simulating the electrical characteristics of digital speakers can operate in one of three modes: measurement and simulation; measurement: i simulate the electrical characteristics ί digital KEYILOY.

In the mode of measuring and simulating the electrical characteristics of digital channels, the input and output of the tested path equipment are connected to the first output and the first input of the device, respectively, and the input and output of the tested equipment of the reception path, respectively, to the second output and second input of the device. At the same time, the following characteristics can be measured in the test equipment: the number of errors, the amount of signal phase jitter, the number of slips, the signal transit time, and the following characteristics are simulated: phase jitter of the transmitted signal, a continuous stream of errors with a given error probability; slippage by a predetermined number of clock cycles, delay of the transmitted signal by a predetermined time. The simulation of these characteristics is carried out by signals from block 20.

In the mode of measurement and simulation of the electrical characteristics of digital channels, the device operates as follows.

The sequence of clock pulses are supplied to the first and second inputs of the sensor 2 jitter phase signal from the second outputs of the generator 1 clock pulses and the input unit 4, respectively. In sensor 2, phase jitter of a given frequency and amplitude can be introduced into one of these sequences. From the output of the sensor 2, a sequence of clock pulses is fed to the input of the sensor 3. Sensor 3 allows you to generate recurrent sequences of different periodicities. From the output of the sensor 3, the signal goes to the first output of the device and then to the input of the tested equipment of the transmission path. From the output of the test equipment of the transmission path, the signal is fed to the first input of the device and then to the input of the input unit 4. The input unit 4 provides coordination of the parameters of the signals at the junction of the tested equipment of the transmission path with the first input of the device, the allocation of the clock frequency from the signal from the tested equipment, conversion input signal into a binary sequence of pulses and generates a clock frequency (from the second output of the input unit 4) to the second clock input of the sensor 2 jitter phase signal through it the output unit 8, as well as on the shaper 5 errors, sensor 6 slippage and block 6 delay. The binary sequence of pulses from the first output of the input unit 4 is supplied to the first inputs of the serially connected shaper 5 errors, sensor 6 slippage, block 7 delay signal and output block 8. Shaper 5 errors provides the superposition of errors on the binary sequence of pulses. C. the output of the shaper 5 information signal is fed to the input of the sensor 6 slippage. From the output of the slippage sensor 6, the signal is supplied to the first input of the delay unit 7, where a predetermined delay of the information signal in time occurs. Next, the information signal is fed to the first input of the output unit 8, the second input of which receives the clock frequency extracted from the information signal in the input unit 4 and passed through the sensor 2 jitter phase signal. The output unit 8 provides coordination of the parameters of the signals at the junction of the tested equipment of the receiving path with the second output of the device for measuring and simulating the electrical characteristics of digital channels. From the output of the test equipment of the reception path, the information signal is fed to the second input of the device and then to the input of the signal phase jitter measuring unit 9, as well as to the first inputs of the slippage detection unit 11, the comparison unit 12, and the clock synchronization unit 14. In block 9, the parasitic phase modulation signal (phase jitter signal) is extracted and its value is indicated.

The sensor 10 of the reference signals generates the same recurrent sequence of pulses from the signals from block 20, as the sensor 3 of the test signals. When the sensor 10 is not phased out in a cycle with the received signal, then the third input of the sensor 10 receives the signal Phase failure from the block 13 cyclic phasing. According to this signal, a received signal (through a sequentially connected clock synchronization unit 14) is supplied to the first input of the sensor 10, which fills the shift register (not shown) of the sensor 10. After its correct filling, the feedback signal and the sensor are closed at the second input of the sensor 10 starts to work autonomously. C. the output of the sensor 10, a recurrent pulse sequence is fed to the inputs of the blocks. 11 and 12. In block 11, inserts or occurrences of characters in the information signal are detected.

In block 12 comparison, which is an adder modulo two, are compared element-wise received signal and the signal from the output of the sensor 10 of the reference signals. When both signals are phased in a cycle, the signal (G) at the output of block 12 corresponds to an error in the received information (in the error measurement mode). In the mode of measuring the signal travel time at the output of block 12, a code combination is entered that is entered in the sensor 3 by the signal from block 20. The output of the comparison block 12 is connected to the input of the error counter 18 and the input of the meter 15.

The counter 19 duration of the measurement sessions sets the operating time and starts the counter 16 slippage and the counter 18 errors on the control signals received at the counter 19 from the control unit 20. The results of measuring the number of slippages, errors, and signal transit time are displayed on the digital display of the display unit 17 upon a command from unit 20. When measuring the transit time, errors and slippage are not measured.

Claims (1)

Claim A device for measuring the simulation of the electrical characteristics of digital channels, containing a slip counter, a test signal sensor, the output of which is the first output of the device, a phasing block, a clock pulse generator connected in series, a clock synchronization block, a reference signal sensor, and a comparison unit. an error counter and a display unit, the second input of which is connected to the output of the slip counter, the first and second outputs of the cyclic phasing unit are connected respectively to the second and third inputs of the reference signal sensor, the second inputs of the clock synchronization unit and the comparison unit are combined, characterized in that, - In order to reduce the measurement time and ensure the measurement of signal phase jitter, a slippage detection unit, a signal phase jitter sensor, a meter for the duration of measurement sessions, and an rhenium phase jitter, an input unit connected in series, the input of which is the first input of the device, an error generating unit, a slippage sensor, a signal delay unit and an output unit, the output of which is the second output of the device and the operation mode setting unit and the signal transit time meter connected in series, output which is connected to the third input of the display unit, the input is connected to the output of the comparison unit, the third input is combined with the information input of the session duration counter measurement and connected to the first output of the clock generator, the second output of which is connected to the first clock input of the signal phase jitter sensor, the second clock input of which is connected to the current output of the input unit and the clock inputs of the error generation unit, slippage sensor and signal delay unit, the information output is connected to the information input of the sensor of test signals, and the clock output is connected to the clock output of the output unit, the output of the meter for the duration of the measurement sessions is connected to the second input of the error counter and the first input of the slip counter, the second input of which is connected to the first output of the slip detection unit, the second and third outputs of which are connected respectively to the first and second inputs of the cyclic phasing unit, the second output of which is connected to the phasing input of the slip detection unit, the first and the second information inputs of which are combined, respectively, with the first and second inputs of the comparison unit, the second input of which is combined with the phase and jitter measuring unit 1699002 is connected to the second input of the device, the second outputs of the operating mode setting unit are connected to the corresponding installation inputs of the reference signal sensor, the third outputs are connected to the corresponding installation inputs of the signal hold unit, the fourth outputs are connected to the corresponding installation inputs of the slip sensor, the fifth outputs are connected to the corresponding installation inputs error generation unit, sixth outputs are connected to the corresponding installation inputs of the test signal sensor, seventh outputs By connecting the respective inputs ustanovoch5 nym jitter sensor signal, eighth outputs connected to respective inputs of the meter mounting duration measurement sessions ninth outputs are connected to inputs sootvetstvu10 yuschim mounting the display unit.