SU1698964A1 - Amplitude former - Google Patents

Abstract

The invention relates to a measurement technique and can be used in a functional control device of digital microcircuits for switching a voltage between predetermined levels of an input of a controlled chip. The purpose of the invention, the expansion of the field of application, is achieved by increasing speed, expanding the range and increasing the accuracy of setting the output signal levels. Separation of the formation and tracking levels of the output signal provides an extension of the output amplitude range. Exclusion of the saturation mode of the transistors of all the elements of the driver and the use of forcing RC circuits provide an increase in speed. 1 s p f-ly, 1 ill.

Description

The invention relates to a measurement technique and can be used in a functional control device of digital microcircuits for switching voltage between predetermined levels at the input of a controlled chip.

The purpose of the invention is to expand the field of application by increasing speed, expanding the range and increasing the accuracy of setting the output signal levels.

The drawing shows a schematic diagram of the amplitude driver.

Amplitude driver contains differential amplifiers 1, 2, 3.4 current switches, output pnp transistor 5, output npn transistor 6, repeaters 7.8 current, diodes 9.10, divider

11 voltages, control buses 12, 13, bus 14 for setting the upper set voltage, bus 15 for setting the lower set voltage, bus 16-20 for power, bus 21, 22 for setting the bias voltage, output bus 23 forformer, resistors 24, 25, accelerating condensates 26, 27.

The direct inputs of the differential amplifiers 1, 2 are connected to buses 14, 15, the inverse inputs are connected to the output of a voltage divider 11, the first outputs are connected to the power terminals of repeaters 7, 8, and buses 19, 20, the second outputs are connected via diodes 9, 10 with the output bus 23 of the driver, the first input of the voltage divider 11 and the collectors of the transistors 5, 6, the emitters of which through

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corresponding resistors 24, 25 are connected to power supply buses 16, 17, the bases are connected to direct outputs of current switches 3.4, the inverse outputs of which are connected to inputs of repeaters 7, 8 current, current switch outputs 3 are connected to power buses 16, 18, conclusions the power of the current switch 4 is connected to the busbars 17, 19; the first inputs of the current switches 3, 4 are connected to the control buses 12, 13; the second inputs are connected to the bias voltage setting bus 21; the inputs of the current level diff. The potential amplifiers 1, 2 are connected to the outputs of the current repeaters 7, 8, the second input of the voltage divider 11 is connected to the bus 22 for setting the bias voltage.

The device works as follows.

At a low level of the control signal at the input of the current switch 3, a voltage is established at its direct output, which unlocks the output pnprtrzistoror 5, through a current-generating circuit connected to its emitter, a current flows from the power bus 16 creating a high level of voltage on the output bus 23. This level, weakened by the voltage divider 11, is fed to the inverting input of the differential amplifier 1, to the input of which the current is set through the repeater 7 the current from the inverse outputs of the current switch 3 is unlocked e. At the same time, the output of the differential amplifier 1 is supplied with a current, the magnitude of which depends on the voltage difference at the inputs of the differential amplifier 1. This current is transmitted through diode 9 to the output bus 23 and subtracted from the collector current of transistor 5, maintaining a high voltage level on bus 23 in accordance with the magnitude of the reference voltage on the bus 14. In this case, the differential amplifier 2 and the transistor b should not produce significant currents on the bus 23, which ensures a low signal level on the bus 13, causing The blocking of the transistor 6 and the minimum current level of the differential amplifier 2 are set through the current repeater 8. Simultaneous switching of the signal levels on the low level buses 12 and 13c to high leads to the locking of the transistor 5, and through the current repeater 7 it reduces the current of the differential amplifier 1 and unlocks the amplifier 2 and transistors 6, which operate similarly to amplifier 1 and transistor 5, but form a low voltage level on bus line 23 in accordance with

the value of the reference voltage on the bus 15. When establishing a high voltage level on the bus 12 and low - on the bus 13 differential amplifiers 1, 2 and

the transistors 5 and 6 are locked, providing the third output state of the device. Diodes 9 and 10 prevent busbar 23 from closing to the inverting inputs of differential amplifiers 1 and 2 through transitions

0 collector is the emitter of the output transistors of these amplifiers. The use of the voltage divider 11 prevents saturation of the output transistors of amplifiers 1 and 2. Through the use of parallel-series RC circuits as current-generating elements in the amplifiers 1, 2 and zmitger load of transistors 5 and 6 the forcing of currents is provided at the moments of switching the output signal levels, which increases the device speed under capacitive load. The constant voltages Ui, Ua, and Oz on the tires 18, 19, 20 ensure the linear operation of the transistors in

5 differential amplifiers 1, 2 and switches S, 4 currents, the bias voltage used on bus 21 sets the average level of control signals on buses 12 and 13. In particular, with V, B, B, 1), 7

0 V and voltages on buses 16 and 17, respectively, 8 V and -3 V on the output bus, a signal is generated with the upper level up to 6 V and the lower level up to -1 V at the lower and upper levels of the control signals (at

5 tires 12 and 13) 0.3 V and 1 8 respectively. The voltage Uc2 of the voltage divider 11 is in the interval between the high and low levels of the output voltage.

0 Separation of the formation and tracking of output signal levels, the use of transistors 5, 6 as power amplifiers and controlled current sources provide an expansion of the output signal amplitude range and stability when working on a capacitive load, which expands the field of application of the imaging unit. The absence of all transistors in the device mode is more than 0 and. The use of boost capacitors in current generators provides an increase in speed. No voltage switching on non-inverting inputs of differential amplifiers

Claims (2)

5 1 and 2 provides low consumption from busbars 14, 15 reference voltages. Claim 1. Amplitude driver, comprising first and second differential amplifiers, the inverse inputs of which are interconnected, the output pnp transistor, the output pnp transistor, the first and second resistors, characterized in that areas of application by increasing the speed, expanding the range and increasing the accuracy of setting the output signal levels; the first and second current switches, the first and second current repeaters, the first and second diodes, the voltage divider, the first the inputs of the first and second current switches are connected to the respective first and second control buses, the second inputs are connected to the first bus of the bias voltage setting, the inverse outputs are connected to the inputs of the corresponding first and second current repeaters, the direct outputs are connected to the bases of the corresponding output pnp transistor and the output npn transistor, the collectors of which are connected to the output bus, the emitters are connected to the corresponding first and second power lines through the corresponding first and second resistors and the first power output of the corresponding first and second current switches, the second power supply terminals of which are connected respectively to the third and fourth power lines, the current level inputs of the first and second differential amplifiers are connected to the outputs of the corresponding current repeaters, the power supply terminals of which are connected to the first outputs of the corresponding first and the second differential amplifiers and the corresponding fourth and fifth power buses, the second outputs of the first and second differential amplifiers th through the respective first and second diodes are connected to the output bus of the driver and the first input of a voltage divider, the second input of which is connected to the second bus of the bias voltage setting, the output the voltage divider is connected to the inverse inputs of the first and second differential amplifiers, the direct inputs of the first and second differential amplifiers are connected respectively to the upper setting voltage setting bus and the lower setting voltage setting bus, the power terminals of the first and second differential amplifiers are connected respectively to the fifth and fourth power tires. 2. The shaper of claim 1, characterized in that the first and second accelerating capacitors are introduced in parallel with the respective first and second resistors.