SU1697225A1 - Method of regulation of voltage of d c link of frequency converter with pulse-duration modulation of output voltage - Google Patents

Abstract

The invention relates to electrical engineering and can be used in systems of an adjustable AC drive. The aim of the invention is to improve the energy and weight and dimensions of the transducers. The method of regulation consists in a stepwise change in the voltage of the DC link, when at the lower level it forms as a three-phase half-wave rectified, at the upper level - a three-phase two-wave rectified, at an average level - specially formed from the segments of linear stresses. 4 il. (L

Description

The invention relates to electrical engineering and can be used in systems of an adjustable AC drive as a power source.

The aim of the invention is to improve the energy and mass-dimensional parameters of a frequency converter with pulse-width modulation of the output voltage.

When the pulse-width modulation of the output voltage of the frequency converter with voltage control varies by the depth of the center of the pulse-width modulation and the voltage of the DC link of Wamax is constant, which is obtained as a three-phase two-wave rectified, if necessary, a significant reduction in the output voltage of the minimum converter Cmin by decreasing the modulation depth to

  Umin / Key UdMaKCi (1)

where Ki is the voltage transfer coefficient of a three-phase autonomous inverter, the harmonic composition of the output voltage and the load current is significantly deteriorated. In this connection, it is advisable to divide the entire range of output voltage regulation into several subranges, in each of which the voltage of the DC link has its constant level, and the output voltage is also controlled by changing the depth of pulse width modulation, but in more limited in

o you

Xi

go yo ate

with the expression (1) on the minimum modulation depth limit, i.e. there is no need to change the modulation depth from / min (1). close to the bee, up to one, as is required with a constant DC link voltage.

The proposed method of controlling the voltage of the DC link of the frequency converter with pulse-width modulation of the output voltage, taking into account the above noted, contains the following operations. If necessary, to obtain the output voltage from the minimum 1) Min to KiUsYin, where Usyin is the minimum voltage at the output of the transmitter, corresponding to the lower voltage level of the DC link, the latter, equal to Shmin, is formed from the positive half-wave of the phase voltages rehfaznogo voltage three-phase network as a half-wave rectified. The depth of the pulse-width modulation of the output voltage at this level of the DC link varies within

Emin / Kiiamin / 1. (2)

When the required voltage at the output of the converter is set to more than Ki11s1min, but not more than KnUdcp, where Uckp is the average voltage level of the DC link, the voltage at the output of the rectifier is formed at each period of the network voltage in series from sinusoids of linear voltages

UAB with Uwe at ftm l / 6; UCA with l / 2} 1. UAB with ftJttf l / 2; 2 UBC with l / 3; 5l / 6: UCA with l / 6; UAB at wts l; 7 UBC at wk | 7 l / 6; 4 UCA at a) 4 l / 3; 3 UAB at (l / 2; 5 UBC at m l / 3; 11 UCA at a); g / 6: 2 l.

d

where w t - 0 corresponds to the beginning of the positive half-period of the phase voltage UA. At this level of rectified voltage, the depth of the pulse-width modulation of the output voltage of the converter varies within

UdMHH / Udcp. (four)

If the required voltage at the output of the converter becomes greater than KnUdrp, the DC link voltage

corresponds to the upper level, and the voltage at the output of the rectifier is formed from the positive and negative half-waves of the linear voltages of the network as a three-phase two-wave rectified. The depth of the pulse-width modulation of the output voltage of the converter at this level of the DC link varies within

Udcp / UdMaKC p 1. (5)

FIG. 1 is a schematic of a device for adjusting the voltage of a DC link of a frequency converter; in fig. 2 - diagram of the work

5 of the output voltage control variable frequency converter; in fig. 3 shows the curves of the supply voltage and the voltage of the DC link: FIG. 4 is a diagram illustrating the operation of the rectifier control unit.

The device for regulating the voltage of the DC link of the frequency converter contains (Fig. 1) a three-phase bridge rectifier, made at fully controlled valves 1, 2, 3, 4, 5. 6. the inputs of which are connected to the terminals 7. 8. 9 phases A, B and C, respectively, of the network, and the outputs through a 10 DC link with an inductive capacitive filter are connected to the input of an autonomous inverter 1 1 with pulse-width modulation of its output voltage, unit 12 of the rectifier control, block 13 adjusting the output voltage of a 5 hour converter oti, system 14 control by an autonomous inverter 11. block 15 setting the output voltage of the converter connected by the output to the input of block 13 of regulation, block 16 setting the frequency of the output

0 voltage converter, the output of which is connected to one of the inputs of the system 14 control autonomous inverter 11 between the clamp 17 of the neutral wire network and

common clamp anode valve group

5 2, 4, 6 an additional fully controlled valve 18 is switched on. Sensors J9, 20, 21 phase voltages A, B. C are connected to the inputs of the first 22, second 23, third 24 active filters whose outputs are connected to the first, the second, third inputs, respectively, of the rectifier control unit 12. The converter voltage regulating unit 13 comprises the first 25, second 26 and third 27 reference blocks

5 voltages, the first 28 and second 29 comparators, to the first inputs of which, as well as to the input of the first 30 and the first input of the second 31 amplifiers, are connected the input of the control unit 13, and the second inputs of the first 28 and second 29 comparators and the second amplifier 31 are connected respectively to the outputs of the first 25, second 26 and third 27 blocks of the reference voltage, respectively. The outputs of the first 30 and second 31 amplifiers and the input of the control unit 13 through the first 32, second 33 and third 34 keys, respectively, are connected to three inputs of the adder 35, the output of which is the first output 36 of the block 13 connected to the second input of the control system 14 of the autonomous inverter 11 The inverse logic output of the first comparator 28 is connected to the first input of the first matching circuit 37, and the direct output to the first inputs of the second 38 and third 39 matching circuits, the second inputs of the first 37 and second 38 matching circuits are connected to the inverse logical output The second comparator 29, the direct output of which is connected to the second input of the third coincidence circuit 39. The output of the first matching circuit 37 is connected to the first input of the first element OR 40 and to the control input of the first key 32, the output of the second matching circuit 38 to the first input of the second element OR 41 and to the controlling input of the second key 33, and the output of the third matching circuit 39 - to the second inputs of the first 40 and second 41 OR elements and to the control input of the third key 34. The outputs of the first coincidence circuit 37, the first 40 and second 41 OR elements are respectively the second 42, the third 43 and the fourth 44 outputs of the control unit 13 and are also fourth m, fifth and sixth inputs of the control unit 12 respectively rectifier. The rectifier control unit contains six from the third 45 to the eighth 50 comparators, twenty one from the fourth 51 to the twenty fourth 71 matching circuit, six from the second 72 to the seventh 77 adders and seven from the first 78 to the seventh 84 power amplifiers, the outputs of which are the outputs of the control unit 12 are connected to the control inputs of the valves 1, 2, 3, 4, 5. 6 and 18, respectively. The first input of the control unit 12 is connected to the first inputs of the third 45, fourth 46 and sixth 48 comparators, the second input to the first inputs of the fifth 47 and eighth 50 and to the second input of the fourth 46 comparators, the third input to the first input of the seventh 49 and second inputs the sixth 48 and the eighth 50 comparators, the second inputs of the third 45, the fifth 47 and the seventh 49 comparators are connected to the terminal 17 of the neutral wire. The direct logic output of the third comparator 45 is connected to the first inputs of the fourth 51, sixth 53, thirteenth 60 and twentieth 67

coincidence circuits, and inverse - with the first inputs of the seventh 54, ninth 56 eleventh 5B and eighteenth 65 coincidence circuits, the direct output of the fourth comparator 5 46 is connected to the second inputs of the sixth 53 and fifteenth 62 schemes of coincidence, and the inverse to the second inputs of virgins the 56 and the tenth 57 coincidence circuits, the direct output of the nth switch 47 is connected to the first inputs 10 of the eighth 55, the tenth 57, the twelfth 59 and the second input of the twentieth 67 coincidence circuits, and the inverse to the first inputs of that 52, fourteenth 61 and the fifteenth 62 and with the second entrance the eighteenth 65

5 matching circuits, the direct output of the sixth comparator 48 is connected to the second inputs of the seventh 54 and sixteenth 63 matching circuits, and the inverse to the second inputs of the fourth 51 and twenty-first 68 circuits

0 matches, the direct output of the seventh comparator 49 is connected to the second inputs of the eighth 55 and thirteenth 60 and to the first inputs of the sixteenth 63rd and seventeenth 64 coincidence circuits, and the inverse to the second

5 inputs of the fifth 52 and eleventh 58 and the first inputs of the nineteenth 66 and twenty-first 68 coincidence circuits, the direct output of the eighth comparator 50 is connected to the second inputs of the twelfth 59 and ninety-six 66 coincidence circuits, and the inverse to the second inputs of the fourteenth 61 and seventeenth 64 match schemes. The outputs of the fourth 51, para. 52, and sixth 53 coincidence circuits are connected to the first three.

5 inputs of the second adder 72. outputs of the seventh 54, eighth 55 and ninth 56 coincidence circuits - with the first three inputs of the third adder 73, outputs of the tenth 57, eleventh 58 and twelfth 59 circuits

0 matches - with the first three inputs of the fourth adder 74, the output of the thirteenth 60, fourteenth 61, and the fifteenth 62 matching schemes - with the first three inputs of the fifth adder 75, the outputs of the sixteenth

5 63, seventeenth 64 and eighteenth 65 coincidence circuits — with the first three inputs of the sixth adder 76, outputs nine nine-six 66, twentieth 67 and twenty-first 68 coincidence circuits — with the first three inputs of the seventh adder 77. The fourth inputs of the second 72, third 73, the fourth 74, the fifth 75, the sixth 76 and the seventh 77 adders are connected to the fifth input 43 of the control unit 12. Outputs of the third 73,

Five fifth 75 and seventh 77 adders are connected to the first inputs of the twenty second 69 respectively. Twenty third 70 and twenty fourth 71 coincidence circuits, the second inputs of which are connected to the sixth input 44 of control unit 12. Outputs

the second 72, fourth 74, sixth 76 adders, twenty-second 69, twenty-third 70 and twenty-fourth 71 coincidence circuits are connected to the inputs of the first 78, third 80 and fifth, respectively, the second 79, fourth 81 and sixth 83 power amplifiers, and input A seventh power amplifier 84 is connected to the fourth input 42 of the rectifier control unit 12.

The device for regulating the voltage of the DC link of the frequency converter with pulse-width modulation of the output voltage operates as follows.

When the relative values of the voltage Uis (with respect to its maximum value, corresponding to the maximum voltage level at the output of the converter) are at the output of task block 15, which in FIG. 2 is represented gradually increasing in time, does not exceed the voltage LJ25 at the output of the first block 25 of the reference voltage, which is typical for the time interval from zero to ti, then, as follows from the diagrams in FIG. 2, where the index of each of the voltages corresponds to the element number in FIG. 1, and the corresponding dependence characterizes the voltage change at the output of this element, the direct logic outputs of the first 28 and second 29 comparators U28 and Uzg present a zero signal. As a result, the signal at the output of the first coincidence circuit 37 Uz, the inputs of which are fed from the inverse logic outputs of the first 28 and second comparators 29, is equal to one, and the signals Uzi and 1) ze at the outputs of the second 38 and third 39 coincidence circuits are zero. This leads to the fact that the signal Sho at the output of the first element OR 40 is equal to one, and the signal U41 at the output of the second element OR 41 is zero, Then at the second 42 and third 43 outputs of the output control unit 13 of the converter voltage, and also at the fourth 42 and the fifth 43 inputs of the rectifier control unit 12 have a single signal, and the fourth output 44 of the unit 13 or the sixth input of the unit 12 has a zero signal. This makes it possible, due to the input of a single signal from the fifth input 43 of block 12 to the fourth inputs from the second 72 to the seventh 77 adders, to have at the outputs single signals and due to the arrival of a zero signal from the sixth input. 44 blocks 12 to one of the inputs of each of the twenty-second 69, twenty-third 70 and twenty-fourth 71 coincidence circuits to have zero signals at the outputs. Then

single signals from the outputs of the second 7.2, fourth 74, sixth 76 adders and from the fourth input 42 of block 12 are fed to the inputs of the first 78, third 80, and the second 82 and

Seventh 84, respectively, power amplifiers, from which the amplified signals are fed to control electrodes, respectively, of the first 1, third 3, fifth 5 and seventh 18 fully adjustable valves and keep them constantly ready for operation - a single-phase uncontrolled straightening a three-phase voltage coming from the terminals 7, 8, 9 of the network. On

5, the output of the rectifier is the voltage corresponding to that shown in FIG. 3, the thickened line, the average value of which corresponds to the minimum level and is equal to

0

UdM,

5 L / W

1BJ

UdM1 ™ ТЗЈ7Т 6и sln «it is 3%. .17 if

(6)

where ift, 1) f - amplitude and acting

5 value of phase mains voltage. In this case, a single signal Uz from the output of the first coincidence circuit 37, which arrives at the control input of the key 32, ensures the arrival of a signal from

0 (solid line in Fig. 2) from the output of the first amplifier 30 to one of the inputs of the adder 35 and then from the first output 36 of the control unit 13 to the input of the system 14 of the control by the autonomous inverter 11. Signal

5 Ouzo characterizes the modulation depth /. inverter output voltage, which, depending on the signal Uis, should vary from the minimum value, "min (1) at the minimum signal Uis

0 to one at the maximum in this mode Uis (as follows from Fig. 2, this corresponds to 0.5). As a result, the gain of the first amplifier is two. In the second, 33 and the third are 34 controlled keys.

5, the control inputs of which in this mode receive the signals Uze and Uze from the outputs of the second 38 and third 39 coincidence circuits, the signals do not pass. The modulation depth in these modes varies within the limits defined by expression (2).

When the voltage Uis at the output of block 15 sets the voltage U25 at the output of the first block 25 of the reference voltage, but less than the voltage U26 at the output of the second

5 of the reference voltage block 26, as follows from the diagrams in FIG. 2, for the corresponding time period ti to t2, a single signal appears at the forward logic output of the first comparator 28

U28, and at the same output of the second comparator 29, the signal U29 remains zero. As a result, the signal from the output of the first circuit 37 coincides with zero, the key 32 ceases to pass signals, the zero signal Uz, coming from the second output 42 of block 13 to the fourth input 42 of block 12 and further to the input of the seventh power amplifier 84, locks the controlled valve 18 .Uze signal from the output of the second circuit.

38 coincidence becomes equal to one, and entering the control input of the second key 33, translates it into a conducting state. 11ze signal from the output of the third circuit

39 coincidence remains zero, and the third key 34 remains in a non-conducting state, the signal U40 at the output of the first element OR 40 becomes equal to zero, and this zero signal from the third output 43 of the block 13 is fed to the fifth input 43 of the block 12 and the fourth the inputs of all adders (from the second 72 to the seventh 77) of the block 12. The signal U41 from the output of the second element OR 41 (FIG. 2) becomes equal to one and from the fourth output 44 of block 13 goes to the sixth input 44 of block 12 and further to the second inputs twenty second 69, twenty third 70 and twenty fourth 71 match schemes . In this mode, due to the presence of a single signal U41 on the second inputs of the twenty-second 69, twenty-third 70, twenty-fourth 71 coincidence circuits and a zero signal Scho on the fourth inputs all from the second 72 to the seventh 77 adders, the order of switching valves 1-6 of the rectifier is determined The signals generated by the logical part of block 12, consisting of six comparators (from the third 45 to the eighth 50) and eighteen coincidence circuits (from the fourth 51 to the twenty-first 68) with the seventh valve closed 18. How. depicted in FIG. 4, the signals U22, U23, U24, proportional to the phase voltages UA, UB, Uc of the network, from the outputs of the first 22, second 23, third 24 active filters, the inputs of which receive signals from sensors 19, 20, 21 phase voltages, and the zero signal from terminal 17 is fed to the inputs of the third 45, fourth 46, p 47, sixth 48, seventh 49, eighth 50 comparators in accordance with the diagram in FIG. 1. On direct and invertor logical outputs

U45-U50 and U45-U50 of these COMPETITORS, the signals shown in FIG. 4. With the help of coincidence circuits (from the fourth 51 to the twenty-first 68), the signals,,,,,, are shown at the outputs of the adders (from the second 72 to the seventh 77), shown in FIG. 4, which from the outputs of the second 72, fourth

74, sixth 76 adders are fed to the inputs of the first 78, third 80 and fifth power amplifiers, respectively, and then to the control terminals of the valves 1, 3 and 5.

the ac outputs of the third 73, p of the 75 and the seventh 77 adders after the twenty-second 69, twenty-third 70 and twenty-fourth 71 coincidence circuits - to the inputs of the second 79, fourth 81 and sixth 83 power amplifiers and further to the expanding terminals of the vents, 2, 4 and 6 respectively. As a result, due to the appropriate switching of the valves at the output of the rectifier, a voltage is generated in the DC link.

5 in accordance with the algorithm (3). which is represented by the thickened line in FIG. 36 and represents the average voltage level of the DC link, and its average value is

0

Udcp 3t7B- J (mt + l / 6)) if, 69U +

(7)

where Uflm beats ifft amplitude of the line voltage network.

In this mode, a signal determining the modulation depth / g and coming from the first output 36 of the unit 13 to the second input of the system 14 of the inverter control 11 is generated as follows. The input of the second amplifier 31 receives a signal Ui5, from which the signal from the output of the third block 27 of the reference voltage is subtracted, the value of which is equal to U25. The result is amplified in the amplifier with a gain factor determined by dividing the maximum

the average value of the voltage at the output of the three-phase full-wave rectifier, which, as is well known, is equal to UdMaKc 2.34 UV, for the result (7), i.e. the gain of the second amplifier is 1.385. As a result, the modulation depth on this gap in accordance with expression (4) varies within 0.692 / and 1 This U31 signal Ozz from the output of the second amplifier 33 (a solid line in Fig. 2) through the key 33 conducting in this mode and the adder 35 is fed to the first output 36 of the output voltage control unit 13,

When the voltage Uis at the output of the unit

The 15 set exceeds the voltage U26 at the output of the second block 26 of the reference voltage and changes to its maximum value (in relative units to y 1), which corresponds to the limits of change in time in FIG. 2 g t tc, the signal Uag at the forward output of the second switch 29, as well as the signal U28 at the forward output of the first switch 28, becomes equal to one. The signal Us at the output of the first coincidence circuit 37 remains zero, the signal of the csz at the output of the second coincidence circuit 38 again becomes zero, and the output signal of the third coincidence circuit 39 becomes equal to one and, at the inputs of the first 40 and second 41 elements OR, provides single signals at the third 43 and fourth 44 outputs of block 13 and respectively on the fifth 43 and sixth 44 inputs of block 12, which in turn ensures the supply of constant single signals from the outputs of the second 72, fourth 74, sixth 76 adders, twenty volts 69, twenty-third 70, twenty-fourth 71 coincidence circuits, which are fed to the inputs of the first 78, third 80, fifth 82, second 79, fourth 81 and sixth 83 power amplifiers, respectively, from the outputs of which constant unlocking signals are received to the control the clamps 1, 3, 5, 2, 4 and 6 of the rectifier with the valve 18 closed. As a result, an uncontrolled three-phase rectifier bridge is operated and a voltage is formed in the DC link represented by the thick line in FIG. Sv and corresponding to the maximum voltage level of the DC link, the average value of which is

Udrnadc / SIn (Mt + JT / 6) dO) t 2.

(eight)

In this mode, the DIB signal from the output of task block 15 is used as the signal determining the modulation depth //, which is provided via a conductive third key 34, which is provided by a single signal U39 from the output of the third coincidence circuit 39 at the control input of the third key 34 and through the adder 35 is fed to the first output 36 of the control unit 13 and to the second input of the system 14 of the inverter control 11. The modulation depth in this mode, as follows from expression (5), varies within 0.722 // 1

As a result, depending on the setting in the DC link, it is possible to obtain three voltage levels, the values of which at these levels are determined by the expressions (6), (7), (8). In this case, the depth of modulation on each of them with the regulating of the output voltage of the inverter 11 and its formation from the voltage coming from the output of the rectifier through the DC link 10, varies within

close to one, which is characterized by the dependence of U35 in FIG. 2 and contributes to the improvement of the voltage form at the output of the inverter 11. The inverter control system 14 with the frequency setting unit 16

the output voltage with a predetermined modulation depth of the pulse-modulated voltage is constructed according to well-known circuits.

The application of the proposed method of regulating the voltage of the DC link of a frequency converter with pulse-width modulation of the output voltage allows

reduce weight and size parameters by eliminating transformers with tap-offs of controlled key elements that provide a step change in the voltage of a constant link

current. At the same time, the energy indicators are also improved by eliminating the electric power losses in the transformer and the controlled keys at the input of the rectifier, which connect it to the necessary tap in this mode.

Claims (1)

transformer. . Invention Formula The method of regulating the voltage of the DC link of the frequency converter with pulse-width modulation of the output voltage, which consists in varying the steps of the voltage at the output of the DC link, in order to improve the power and mass-dimensional parameters of the converter, the voltage at the output of the DC link at the lower stage, corresponding to its lower level, is formed from positive the half-wave phase voltages of a three-phase voltage supplying the DC link, at the upper stage corresponding to its upper level, are from positive and negative half-waves of linear voltages as a three-phase two-wave rectified and at the middle stage corresponding to the average voltage level, - on each period of the supply voltage sequentially from the sections 5 sinusoids of linear voltage UAB on the interval. L / 6, -Vwe on the interval w tЈ / 6. l / 3, UAB on the interval .tg / 2 2l / 3 -UcA on the interval / 3. l UBC on the interval / 6; 4l / s -UAB on the interval a) f. H / 2; 5l: / 3) and UCA in the interval cot t 11l / 6; 2 -UCA on the interval / 3: / 2; UBC on the onfc 2/3 interval; 5 5. corresponds to the beginning of the positive field -UAB on the interval / 6; the phase voltage test period UA. UCA on the interval (/ 3; H / 2; -Uva on the interval / 3; 11 ng / 6 where a) I O corresponds to the beginning of the positive field of the phase voltage uperiod UA. UCA on the interval (/ 3; H / 2; -Uva on the interval / 3; 11 tg / 6. Where a) I O T 19 20 Fig. / ."-."but five . H1. sC i q 5 "S1 5 (5" U J sf yl I-it from & y NJ (L