SU1697118A1 - Method of data reading out of field transistor-based memory members and readout signals shaper - Google Patents

Abstract

The invention relates to computing and microelectronics and can be used in the development of reprogrammed permanent memory devices of large information capacity. The purpose of the invention is to increase the reliability of reading information. The goal is achieved by applying readout control signals to the source in the direction blocking the memory element and changing its amplitude in proportion to the change of the threshold memory element level until it reaches zero and provides the extension of the threshold voltage value, exclusion from the memory cell of the address transistor. 1 Cpfla, 1 Il.

Description

The invention relates to computing and microelectronics and can be used in the development of electrically erasable programmable permanent storage devices (EEPROM) of large information capacity.

The purpose of the invention is to increase the reliability of reading information.

The drawing shows the electrical circuit of the read signal generator.

The shaper contains a second key transistor 1 with an n-type channel, the first current-setting transistor 2 with a p-type channel, a third key transistor 3 with a p-type channel, a reference transistor 4 with an n-type channel, the second current-setting transistor 5 with a p channel -type, third current-setting transistor 6 with n-type channel, cumulative transistor 7 with n-type channel, first key transistor 8 with n-type channel, power supply bus 9, zero potential bus 10, output 11.

A method for reading information from memory elements on field effect transistors is as follows. The memory element is an n-channel MOSFET. To read information from it, a positive voltage relative to the substrate, for example, 2 V and 4 V, respectively, is supplied to the drain and the gate, and a voltage of the same polarity as the gate and drain is applied to the source. In this case, the voltage at the source of the memory element is the blocking pn-junction source-substrate. This voltage varies in proportion to the change in the threshold voltage of the memory element. When reading information, the change in the threshold voltage of the memory element occurs due to the change in charge in the area of substrate depletion and does not change the value of the information charge.

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memory element as well as its logical state. The change in the threshold voltage of the memory element is limited to zero to prevent false reading of information from neighboring unselected memory elements (at the gate of which the voltage is zero), through which current can also flow if the threshold voltage of these elements -channel technology) as a result of erasing information will take negative values.

When a source is connected to a voltage in the direction blocking the memory element (t, that is, the threshold voltage increasing it), its threshold voltage increases. In this case, the low threshold voltage from the negative (for n-channel devices) becomes zero.

A method of reading information from memory elements on field effect transistors can be implemented using a read signal generator. The shaper works as follows.

In the process of erasing information, the threshold voltage of the reference transistor 4 becomes negative.

The selection of the geometrical dimensions of transistors 2 and 4 ensures that in this case the potential at node A becomes lower than the lock potential of transistor 8 and output 11 starts charging from power supply bus 9 through transistors 1.5, and the size of transistor 5 is controlled by current (time constant charge output 11) With an increase in voltage at output 11, and hence at the source of transistor 4, the threshold voltage of the latter increases and, when a certain value is reached, becomes zero. The transistor 4 (the reference memory element) is closed, and the potential at the node A becomes equal to the supply voltage, which is sufficient for locking the transistor 3.

As a result, the potential of output 11 begins to decrease due to the discharge of the capacitance of transistor 7 through the open channel of transistor 6. The discharge current (constant discharge time) is controlled by selecting the geometric dimensions of transistor 6. As soon as the voltage at output 11 reaches a value sufficient the transistor 4. the potential at node A decreases, and the output capacitance 11 begins to charge again, i.e. the voltage at output 11 begins to increase. Thus, the magnitude of the output voltage 11 is maintained at a certain predetermined level determined by the level of the threshold voltage of the transistor 4,

Claims (2)

The output 11 is connected by the control circuit to the sources of storage elements of the storage array matrix in read mode. Invention Formula 51. The method of reading information from memory elements on field-effect transistors, including the formation on the electrodes of the gate and drain of a memory element constant voltage levels relative to the voltage on the substrate and the definition of information stored in the memory element, according to the current flowing through the memory element that differs in order to increase reliability 15 of reading information, simultaneously with the formation of constant voltage levels at the electrodes of the drain and the gate of the memory element, the voltage of the same is applied to the source electrode of the memory element. 20 polarities with respect to the voltage on the substrate, as on the drain electrodes and the gate of the memory element, change the voltage on the source electrode of the memory element proportional to the change in the threshold voltage of the 25 memory element until it reaches zero. 2. A read signal driver containing the first and second n-type key transistors, the third 30 p-type key transistor, the first and second current-driving transistors with the p-type channel, the third current-setting transistor with the n-type channel, the cumulative transistor with n-type channel, the reference transistor with the n-type channel, the drain of which is connected to gates of the first and third key transistors and the drain of the first current-setting transistor, the source of which is connected to the source of the third key 40 of the transistor and connected to the driver power supply bus, and the gate is connected to the gate of the reference key transistor, the drain of the third key transistor is connected to the drain of the first key transistor, 45 whose source is connected to the zero potential bus of the driver and is connected to the source of the storage transistor and the source of the third current-setting transistor, whose drain is connected to the drain of the second 50 current-setting transistor, the gate of which is connected to the drain of the storage transistor, characterized in that the drain and the gate of the second key transistor are connected to the source and drain of the third 55 of the key transistor, respectively, and the source is connected to the source of the second current-setting transistor, the drain of which is connected to 6 by the source of the reference transistor, the gate of the storage transistor and is the output of the driver, and the gate is connected to the gate of the reference transistor and the source of the third current-setting transistor, the gate of which is connected to the drain of the second key transistor. No eleven -ABOUT one Jg 7 387 -about