SU1691968A2 - Digital data communication system with intermediate storing - Google Patents

Abstract

The invention relates to communication technology and can be used in the transmission of discrete information between subscribers, as well as in networks with packet-switched communications and messages. The aim of the invention is to increase the information content. The device comprises a receiver 6, a demodulator 7, a decoder 8, a coding block 9, a modulator 10 a transmitter 11, a queuing block 1, a storage block 2, an analysis block 3, a block 4 for determining the optimal message length, a driver 5 read signals, a mode switching unit 13, an OR 14 element, a message format driver 12. The goal is achieved by forming a message whose length is as close as possible to the optimal value. 1 з.п f-ly 4 Il.

Description

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The invention relates to communication technology and can be used in the transmission of discrete information between subscribers, as well as in networks with packet-switched communications and messages.

The aim of the invention is to increase the information content of the system.

FIG. 1 shows a block diagram of a system for transmitting discrete information; in FIG. 2, the block diagram of the block is known; in fig. 3 is a block diagram of a mode switching unit; in fig. 4 shows the flow diagrams of the message format generator.

The transmission system (Fig. 1 consists of block 1 of the queue, storage unit 2, analysis block 3, block 4 for determining the optimal message length, read signal generator 5, receiver b, demodulator 7, decoder 8, encoding block 9, modulator 10, the transmitter 11, the driver 12 of the message format, the mode switching unit 13, and the element OR 14.

The analysis unit consists of reversible counters 15i-l5n, comparison elements 16i-16n, a signal builder 17, a subtractor estimator 18, a subtractor 19, a counter 20, a register 21. In FIG. 2, an additional output 22 and the first and second additional outputs 23 and 24 of the analysis unit are indicated.

The mode switching unit 4 comprises a trigger 25, elements AND 26 and 27, a counter 28 and a signal conditioner 29. The output element And 6 (output 30) and the output 31 of the imaging unit 29 are connected to the inputs of the imaging unit 12.

The message format former 12 includes a register 32 and counters 33i-33n.

The system works as follows.

The operation of the transmission system is based on the principle of combining packets with predetermined gradations of length into a single communication transmitted via a communication channel. Combining packets into a message is such that the length of the message as a whole is maximally close to the optimal length defined in block 4. The possibility of combining (gluing or mathematical concatenation formulation) of packets into a message significantly expands the range of lengths of the transmitted block of information in accordance with requirements of optimality. So, if the optimal length corresponds to a certain gradation of a packet, but this packet is not in the storage unit, but there are two packets that are half the length, then the device sends both links to the communication channel

These packets are connected to one another, and thus transmits a message (the message in our case is received as a set of packets sent to the communication channel in one transmission session) with the optimal length. At the same time, the prototype device transmits only one of these packets to the communication channel and the difference between the actual length of the information block and the optimal length is half the optimal length.

From sources of information or switching equipment, block 1 receives packets intended for transmission over communication channels. In block 1, the length of the received packet is determined. Depending on the length of each received packet, they are recorded in a storage unit, consisting generally of η autonomous storage units, each of which stores packets of a certain length. Suppose there are n packet length gradations.

The appearance of the packet of the i-th gradation of length is recorded in the corresponding 1st sub-block of the storage unit, and from its output to the input of the reversible counter 15i of the analysis unit a signal arrives, resulting in the contents of this counter increasing by one, which corresponds to the current time 1st gradation contained in the storage unit.

If the corresponding reversible counter is in the zero state, this means that there are no packets of this gradation in the current block of time, and the signal from the counter to the comparison device is not received. If the counter is in a state other than zero, then a signal is sent to the corresponding comparison device from it, which is used to allow the operation of this comparison device.

At the receiver output of the system, a feedback signal is received from the receiving side (not shown, as well as the input switching equipment), the feedback code combination that goes to the demodulator and then to the decoder, in which the code is decoded feedback combinations.

From the outputs of block 4, code 3 enters block 3 (for example, in binary form) corresponding to the optimal message length.

Let us consider in more detail the operation of block 3. In block 3, for each current value of the optimal length of the message, the strategy of forming the output message is determined, depending also on the presence and

the number of packets of different gradations in the storage unit.

Suppose that block 3 (like the system as a whole) starts operation from the moment it enters it from block 4 of the binary equivalent of the optimal message length. The trigger 25 is in the zero state, and the clock pulses through the element 27 on the enable signal from the inverse output of the trigger 25 are sent to the analysis block 3 at input 23. In the register 21, the code of the optimal message length is received from block 4 (hereinafter under the length codes we mean their binary equivalents). The counters 18 and 20 in the initial state are in the zero state.

The subtractor 19 subtracts the code of the optimal length of the message and the current length of the message generated for transmission, the contents of counter 20 being subtracted from the contents of register 21. The difference in the form of a binary code goes in parallel to all the comparison blocks.

The resolving signal of the corresponding reversible counter (the signal appears if block 2 has a packet of this gradation) in the corresponding element of comparison 16 a binary equivalent of the length code of this gradation is formed and this code is subtracted from the code received from subtractor 19. Subtraction is carried out taking into account the signs of binary codes. If currently in block 2 there are no packets of a given gradation, then the signal c from the corresponding counter inhibits the operation of the element of comparison 16.

The difference codes from the comparison element 16 (they actually also perform the subtraction operation) in the presence of the enabling signals from the corresponding counters J5 arrive at the shaper 17, in which the minimum difference value is determined, and the signs of the differences are analyzed. At any given time, the signal occurs only at one output of the decoder of the driver 17. There are no signals at the other outputs.

At the moment of arrival of the code of the optimal message length (since the zero code arrives from the counter 20 to the subtractor 19) the signals at the output of the counter 20 will be the same as at its descent. These signals are sent to comparison blocks 16. The differences between the optimal length code and the packet codes that are currently present in block 2 are sent to the driver- 17. The signal of the minimum difference from the corresponding output of the driver 17 goes to counter 18, which

is set to the state corresponding to the length of the packet that is closest to the optimal length, the code of which is contained in register 21. The same signal is used to output through the block 5 to form the corresponding packet to the communication channel, as well as counter 33i s shaper 12. In addition, the same

0, the signal subtracts the unit from the contents of the reversible counter 15j. corresponding to the gradation of length, the packet from which is sent to the communication channel. With the arrival of clock pulses

5 counter 18 works on subtraction, counter 20 - on addition. Upon completion of issuing a packet of this gradation, the counter 18, when set to the zero state, issues an enabling signal for the next comparison to the driver 17. At this point, the counter 20 contains the code of the length (current) of the message sent to the communication channel. The process then repeats.

The process of forming the output communication is completed — then, after the next setting of the counter 18, all inputs of the driver 17 are received in the zero state or negative signals (this is determined by the corresponding values of the sign bits from the elements 16). or there are no signals from elements 16 (which indicates the absence of 2 packets of this gradation in block 2). In this case (in other words, if at least one positive signal is missing at the inputs of the driver 17 of all allowed), the frontier 17 at the output 22 outputs a signal to the block 13, which fixes the message to the communication channel to the maximum of the approximate length to the optimal one, and switches the input of the communication channel (in this case, block 9) to the driver 12. At the same time, the signal from the trigger 25 on the input 24 sets the zero state to the zero state.

The clock pulses start to flow to the counter (the counting module of which corresponds to the length of the control word necessary to break the (unambiguous) message into packets on the receiving side). Simultaneously, the clock pulses arrive at the driver 12 (the register 32). Before this signal from the inverse output of the trigger 25 on output 31, the contents of the counters 33 are copied to register 32 and the counters 33 are reset, the register 32 has the equal size of the counters 33 and the counter-counting module 28. With clock pulses in the register shift mode 32 communication channel through

the element OR 14 enters the service word.

After issuing the control word to the communication channel, the signal from the counter 28 causes the driver 29 to generate a signal that switches the trigger 25 into the mode of issuing an information message.

Next, the transmission cycle of the information message is collected, which is collected from packets of different gradations contained in the storage unit. When a different value of the optimal message length arrives from the feedback channel, a transition to a new optimal value is made at any time. At the same time, the system does not lose its working capacity, which can be traced by analyzing its operation in accordance with the algorithm described above.

Consider the work of the system on a specific example. Let at the current time with three gradations of packet lengths () the contents of counters 15 be as follows (we denote eroai: ai 2,,. of the analysis block when concatenating packets into a formed message. The contents of the counters 33 are denoted by cij. Suppose also that the maximum number of packets of each gradation that can be contained in the storage unit is three, thus, the counters 15 and 33 are two-bit, the register 32 and Respectively, the counting unit of the counter 28 is equal to the product of the number of gradations and the size of the counters 33, in our case 6. Suppose also that at a given time from the communication channel the value of the optimal message length is equal to 12. Description of the system will be done in decimal The code of the corresponding values, however, taking into account that the implementation of all devices is simpler when using the binary equivalent of the corresponding numbers, we use the decimal values for simplicity.

When the specified optimal length of the message (12) arrives at the initial zero content of the counter 20, this number comes from the output of the subtractor 19. The following elements are removed from the corresponding elements 16:,, (the x sign means that since the packets of this gradation are (s) in block 2 no, from the corresponding element 162, the signal to the driver 17 is not received).

Since the minimum difference is, according to the signal from the generator 17, the counter 18 is set to state 8, during its operation the change in the state of the generator 17 is blocked, the signal from the generator 17 also arrives

to counter 15i and decreasing its content to a unit (now it is 1), the same signal increases by one the contents of counter 33i (now it is equal to p., while), and enables the issue

0 of the corresponding packet length in the communication channel.

After the counter 18 is set to zero, the driver 17 opens, and the contents of the counter 20 is 8,

5 of the device 19, the difference is 12-8 4; from the corresponding comparison devices, the following codes are received in the driver 17:,, Shaper

17 generates a signal at the minimum difference of 0 (), sets the counter 18c

state 2 and performs the above operations with blocks corresponding to the third gradation of the packet length.

In the third stage, the contents of the counter

5 20 is 10 of the difference of element 16 - respectively:,,, the contents of the counter 33 - respectively:,,, the output of the third gradation packet goes to the communication channel, and the content of the ZZz counter increases to i value.

After the next zeroing of the counter

18c outputs of the elements 16 in the shaper 17 receives signals, respectively: bi4

5 8,, which causes the appearance of a signal at the output 22 of the former 17. This signal switches the trigger 25, reads the contents of the counters 33 into the register 32, as a result, the register 32 records the number

About 1-0-2 or in binary code - 010010 and it enters the communication channel as an official word for dividing the complex message into packets on the receiving side. In addition, the counters 33 are set in a zero state. At the time of issuing the service word, the access of the clock pulses to the analysis block is stopped and resolved again only after its completion, and the analysis and formation of the new information word begins again.

A situation is possible when the minimum difference has a negative value. In this case, the difference sign is irrelevant to the selection of the next packet,

5 attached to the complex message of this cycle. If some gradation coincides exactly with the remaining difference to the optimal length, the corresponding difference is zero, it is this gradation that is used for connection. If a

several differences have the same value at some moment of analysis, then the packet with the longest length is chosen for connection (generally speaking, only two differences from blocks 16 can have the same value at any moment, and one of them is necessarily negative, and the other is positive).

Claims (2)

The invention provides the optimal length of the transmitted message, which increases the information content of the system, claims 1. The system for transferring discrete information with intermediate accumulation according to the author. St. No. 1040620, characterized in that, in order to increase the information content, a mode switching unit, an OR element and a message format driver are entered into it, an OR element is connected between the memory block output and the encoder block input, an additional the analysis unit is connected to the input of the mode switching unit, the first and second outputs of which are connected respectively to the first and second additional inputs of the analysis unit, the outputs of the group of the mode switching unit are connected to the input Am first group shaper co communication format, the output of which is connected to the second input of the OR gate, the outputs block The analysis is connected to the inputs of the second group of the message format generator. 2. The system of claim 1, wherein the analysis unit comprises reversible counters, comparison elements, a counter, a subtracting counter, a register, a feeder, a signal conditioner, reversible counter inputs are the inputs of the first group of the block, the output of each reversible counter is connected to the input of the corresponding comparison element, the inputs of the register are the inputs of the second group of the block, the outputs of the register are connected to the first inputs of the subtractor, the outputs of which are connected to the corresponding inputs of the group of each element of the comparison, outputs which are connected to the corresponding information inputs of the signal generator, the counter outputs are connected to the second inputs of the subtractor, the outputs of the signal conditioning group are connected to the corresponding setup inputs of all reversible meters and the inputs of the subtracting counter group and the outputs of the subtracting counter are connected to the control input of the signal conditioning generator whose output is the auxiliary output of the block, the first input of the counter is the first auxiliary input of the block, the second input is This is combined with the input of the subtracting counter and is the second additional input of the block. cshg ffj) 1L Tff I 25 R f l / # 51P 30 Fm.z FIG. four 28 2g