SU1690210A1 - Data transmission and reception system with packet switching - Google Patents

Abstract

This invention relates to a digital communication technique. The purpose of the invention is to increase the capacity and reduce the average time for receiving information. The system for transmitting and receiving information with packet switching contains on the transmitter side (MS) an encoder 8, a receiver 9 of feedback signals, an input register 1, a block 3 for the primary transmission of information blocks and an OR 6 element, and on the receiving side (ORS) error detection unit 12, element 14, transmitter 13 of feedback signals, element 15 and buffer buffer 10. The goal is achieved by introducing 2 information block numbers, an analyzer 4 feedback signals, a master oscillator 5, a retransmission node 7 on the MS shaper info of the readout block of the received number of the information block, comparison block 16, analyzer 17 of the received information blocks, shaper 18 of the expected number of the information block, block 19 for the allocation of the missing numbers of the information blocks. The system carries out cyclic repeated transmission of unconfirmed information on the MS blocks (IB) during periods of pauses in the flow of information from the source of messages and the issuance of IB to the IRS without arranging their sequence. 1 il. SO with

Description

BY INVENTIONS AND DISCOVERIES

UNION OF THE SOVIET SOCIALIST REPUBLIC., “SU.,” 1690210 A1 (51) 5 _N 04 · L 12/56. 1/12 ___________

AT SCST USSR

DESCRIPTION OF THE INVENTION h

TO AUTHOR'S CERTIFICATE (21) 4610267/09 (22) 11.25.88 (46) 11.11.91. Bull. No. 41 (72) V.A. Gorsky, M. A. Grigoriev, A. G. Mikutsky and V. S. Kozyrenko (53) 621.394.14 (088.8) (56) USSR Copyright Certificate No. 650243, cl. H 04 L 1/10, 1976.

(54) A TRANSMISSION AND RECEIVING SYSTEM FOR INFORMATION WITH PACKAGE COMMUTATION (57) The invention relates to digital communications technology. The purpose of the invention is to increase throughput and reduce the average time for receiving information. The system for transmitting and receiving information with packet switching contains an encoder 8 on the transmitting side (PS), a feedback signal receiver 9, an input register 1, an information block primary transmission unit 3 and an OR element 6. and on the receiving side (OR), a detection unit 12 errors, AND element 14, feedback signal transmitter 13, OR element 15, and buffer storage 10. The goal is achieved by introducing 2 information block numbers, an analyzer 4 of feedback signals, a generator 5, and a retransmission node 7 s blocks, and at block 11 the search PRS received number information unit, the comparison unit 16, analyzer 17, the received information blocks 18 shaper expected information unit number allocating unit 19 missed numbers the information blocks. The system performs cyclic retransmission of unacknowledged information blocks (IS) to the PS during periods of pauses in the flow of information from the message source and the issuance of information to the ISS without ordering their sequence. 1 ill.

IV 0120691 ’ns

The invention relates to digital communication technology and can be used to organize communication between switching nodes.

The aim of the invention is to increase throughput and reduce the average time for receiving information.

The drawing shows a structural electrical diagram of a system for transmitting and receiving information with packet switching.

The packet-switched information transmission and reception system comprises an input register 1, a shaper 2 of information block numbers, a primary information block 3 of the information blocks, a feedback analyzer 4, a generator 5, an OR 5 element, a retransmission node 7, on the transmitting side information blocks, encoder 8, feedback signal receiver 9, and on the receiving side, a buffer storage 10, a block 11 for finding a received information block number, an error detection block 12, a transmitter: 13 feedback signals, elem Entent AND 14, OR element 15, comparison unit 16, analyzer 17 of received information blocks, former of expected information block number 18 and block 19 for missing information block numbers, and the primary transmission unit 3 of the information blocks includes a control unit 20, a buffer storage 21 information blocks and the element And 22, and the structure of the retransmission node 7 of the information blocks includes a control unit 23, a buffer drive 24 information, blocks and element And 25.

The system for transmitting and receiving information with packet switching operates as follows.

The transfer begins with the recording of the information array from the message source through the input register 1 to the shaper 2 numbers, which controls the ability to organize the transfer of this array and. if this is possible, assigns a serial number to it, turning it into an information block, it is impossible to organize a transfer if at least one of the buffer drives 21 or 24 is full. In this case, the control unit 20 or 23 gives a signal to the OR element 6. The output signal of which does not allow recording the information array in the input register 1 from the message source,

If it is possible to organize the transfer of this array, the shaper of 2 numbers transmits a signal to the control unit 20, by which it organizes the recording of the generated information block into the buffer storage 21. The control unit 20 determines the address of the cell to which it is necessary to record, reports it to the buffer storage 23, generates a strobe recording pulse, and the information block from the number shaper 2 is recorded in the buffer storage 21,

The operation of all nodes on the transmitting side is synchronized by the master oscillator 5. It sends a clock signal to the control unit 20, upon receipt of which the latter organizes the issuance of the next information block to the communication channel. It generates the address of the cell in the buffer storage 21, from which information should be read, and also gives a signal to the element And 22, opening it. The information block from the indicated cell of the buffer storage 21 through the element And 22 is supplied to the encoder 8 and then to the communication channel. The control unit 23 generates a cell address in the buffer storage 24, where simultaneously with the output to the encoder 8 from the buffer storage 21, the transmitted information block will be recorded by the gate signal generated by the control unit 23. Thus, in the buffer drive 24, an information block issued to the communication channel is recorded.

From the output of the communication channel, the transmitted • information block is recorded in the error detection block 12, where one of two decisions is made: either the block is erased or fed for further processing. In this case, in case of error-free reception, the number of the received information block is transmitted to the transmitter-13 , which is recorded on the feedback channel and the receiver 9. In the receiver 9 of the feedback signals in relation to the feedback signals, one of the decisions is made: in case of detection of errors, it is erased, in case of error-free reception of the signal Confirmation is supplied for further processing to the analyzer 4. In this case, receiver 9 outputs a feedback signal to the analyzer signal 4, whereby the latter sees to it transmitted signal 'confirmed. He searches for the buffer drive 24 of the information block with this number and erases it.

Repeated transmission of unconfirmed information blocks is carried out using the control unit 23 at time intervals when one of the buffer drives 21 or 24 would be full, or at times when the buffer drive 21 is empty. The buffer overflow signal is generated directly in the control unit 23, and the overflow or flush signal is generated by the control unit 20 and transmitted to the control unit 23.

Having found one of these signals, the control unit transmits an opening signal to the And 25 element and sequentially generates and transmits to the buffer memory cell addresses from which information blocks are sequentially read through the And 25 element to the encoder 8 and then to the communication channel. In this case, the operation of the control unit 23 is synchronized with the communication channel using the master oscillator 5. This allows the analyzer 4 to organize overwriting of information in the drive 24 at the time of its output to the channel. The analyzer 4 performs its work at time intervals between the moments of the output of information blocks to the encoder 8. These periods are also determined by the master oscillator 5, which generates a signal from the analyzer 4 that is inverse with respect to the clock signal supplied to the control units 20 and 23. The procedure for issuing information to the recipient on the receiving side from the error detection unit 12 is determined by the operation of the analyzer 17 of the received information block numbers, which is prepared for operation by signals received from the error detection block 12 and from the shaper 18 of the expected number of the information block, which stores a value at each time numbers of the expected information block and transmits. him to block 16 comparison.

Expected is a number whose reception does not cause disorder in the entire sequence of received information blocks. For example, if information blocks with numbers 1, 2, and 5 are currently accepted, then the information block with number 3 is expected. Actually, the smallest number from the number of unaccepted information blocks is expected.

If the number of the received information block does not match the expected one, then from the comparison block 16 a signal is sent to the received number search block 11, which searches for the received number in the buffer storage 10. The buffer, the storage 10 is filled using the missing numbers allocation unit 19 in this way so that only numbers of those information blocks that were skipped on the receiving steron were recorded in it, i.e. those numbers are stored there that, due to errors, were not received by the error detection unit 12. Therefore, if the block 11 search for the received number detects in the buffer storage device 10 a number equal to the newly received one, this means that the information block with this number was expected to be received, but was not received due to errors. Thus, decisions are made that this information block is accepted without errors for the first time and it is issued to the recipient by applying an OR element 15 to the second input. This signal opens the And 14 element, and the received information block is issued to the recipient. Od. at the same time, the received number is erased from the buffer storage 10.

If the newly received number, not equal to the expected one, is not found in the buffer storage 10, a signal is sent to the analyzer 17, where a decision is made whether it was received for the first time or if it had already been received without errors.

Firstly, the so-called window control is carried out. A window is the number of information blocks, the simultaneous passage of which in the system can be fixed by the receiver. In other words, this is the space of numbers that can be processed at the moment.

The smallest window number is the expected number, the largest is different from it by N, where N is half the numbering module. Thus, window control is a procedure that ensures that the received number fits within the allowed range. For its operation, the value of the upper edge of the window is stored in the shaper 18 of the expected number, i.e. the largest number in the window. As the expected number (i.e., the bottom edge of the window) changes, the top edge also changes.

All received information blocks, whose numbers do not fall into the window, are discarded, as they are considered received again.

Window control alone does not provide protection against the possibility of multiple messages to the recipient of the same information block. It is necessary to identify the situation when the information block located within the window is received correctly several times. For this purpose, the highest received number is stored in the analyzer of received numbers. If the newly received block has a number that is not equal to the expected, but not greater than the maximum received, then it is unambiguously considered that this block is re-received (since its number is not greater than the maximum

Ого received, this means that it has already been transmitted, and if there are no missed numbers in the buffer, then it has already been issued to the recipient).

If the number of the received block is greater than the maximum received, then this means that it first appeared at the reception and should be issued to the recipient.

Thus, the number of the received block can lie in one of the following intervals: in the range of numbers not falling into the window (in this case, the block is erased), the range of numbers from the expected to the maximum received is inclusive (in this case, the block is erased) from the maximum received to the top edge of the window. In this case, the block is issued to the recipient, and the numbers from the maximum to the received are fixed in the buffer storage '10 as not received. The accepted number becomes the maximum.

Analysis on the belonging of the received number to one of these intervals is performed only if it is not detected in the buffer storage 10.

The analyzer's task of '17 received numbers is to determine the interval in which the received number lies and issue a command to carry out the corresponding actions.

Thus, if the number is not found, the corresponding block is issued to the recipient only if this number lies in the range from the maximum received to the top edge of the window. If a number is found in the missed numbers buffer, then it probably has a value less than the maximum accepted, therefore, no new commits are made on it.

The information block is erased by applying a signal to the second input of the error detection block 12.

If the newly received information block has a number greater than the maximum received, then the analyzer 17, having detected such a situation, gives a signal to the block of missed numbers allocation 19, which records 10 numbers in the buffer storage lying in the interval from the maximum stored in the analyzer 17, to the number of the newly received information block. The maximum number is the number of the newly received information block.

Shaper 18 of the expected number stores the smallest unaccepted number, which is considered expected. In case of receiving an information block with a number equal to the expected, it is necessary to form a new expected number. For this, the expected number generator 18 selects the smallest number stored in the buffer storage 10, which is taken as the expected one. If the buffer drive 10 is empty, then the expected number is one greater than the maximum received number stored in the analyzer 17 (when the drive 10 is empty, then the corresponding signal is sent to blocks 18 and 19 from the received number search unit 11, where monitoring is carried out) )

Block 19 allocation of missed numbers, recording in the buffer drive 10 of all numbers in the range from maximum to received, transmits to block 11 search for received numbers a signal by which this block notes that another recording has occurred. Due to this, the received number search unit 11 always has information about the number of occupied cells in the buffer storage 10.

Thus, in the system, on the transmitting side, cyclic retransmission of unconfirmed information blocks is carried out during pauses in the flow of information from the message source and the receiving side receives correctly received information blocks on the receiving side without ordering their sequence. At the same time, the buffer drive 10, the received number search unit 11, the analyzer 17, the shaper 18, and the missed number allocation unit 19 provide protection against issuing the recipient of duplicate messages, as well as from missing information blocks in an unordered sequence.

Claims (1)

Claim A packet-switched information transmission and reception system comprising a encoder on the transmitting side, the output of which is an input of a communication channel, a feedback signal receiver, whose input is an output of a feedback channel, an input register, a serial block of primary transmission of information blocks and an OR element, and on the receiving side, there is a series-connected error detection unit and an element And, as well as a feedback signal transmitter, the input of which is connected to the Feedback signal output of the detection unit error correction, the input of which is the output of the communication channel, and the output of the feedback signal transmitter is the input of the feedback channel, as well as an OR element and a buffer storage device, characterized in that, in order to increase throughput and reduce the average time of receiving information on the transmitting side a block for the formation of serial numbers of information blocks, a block for retransmission of information blocks, identical to the block for the primary transmission of information blocks, specifying a generator and analysis, were introduced feedback signals, while the output of the feedback signal receiver is connected to the first information input of the feedback signal analyzer, to the clock input of which the first output of the master oscillator is connected, the second output of which is connected to the clock inputs of the block of the primary transmission of information blocks and the block of retransmission of information blocks , 15 information outputs of which are connected to the input of the encoder, the output of the signal overflow block retransmission of information blocks through the element OR is connected to the input of resetting the input of the 20th register, the output of which is through the formation unit and the first information input of the comparison unit, into the mountain information and gate inputs of which are connected by the output of service signals and the gate output of the error detection unit, information. the gate and service inputs, the blocking input, and the installation input of the search unit for the received information block number are connected respectively to the service signal output and the gate output of the error detection block, to the input of the buffer storage, to the blocking output of the block for highlighting missing information block numbers and to the first output of the comparison block , the second output of which is connected to the first input of the OR element and the start input of the shaper of the expected number of the information block, the service, control and signal the input inputs of which the serial numbers of information blocks are connected to the gating input and to the information input of the primary transmission block of information blocks, the information output and control output of which are connected to the corresponding inputs of the retransmission block of information blocks, the outputs of which are connected to the second information and control inputs of the feedback signal analyzer communication with the control input of the block of the primary transmission of information blocks, and the output of the signal analyzer s feedback is coupled to the input of the search block retransmission information units, and on the reception side administered block comparison. nomenclature, the search unit for the received information block number, the analyzer of the received information blocks, the block for highlighting the missing numbers of the information blocks and the shaper of the expected number of the information block, while the gate output, the start output, · 45 control and information outputs of the shaper of the expected number of the information block are connected respectively to the input buffer drive, the control input of the analyzer of the received information blocks, the starting input of the search unit of the received number of