SU1679615A1 - Comparator - Google Patents

Description

The invention relates to radio engineering and is intended for use in analog-to-digital converters with high resolution. The purpose of the invention is to increase the gain and speed. The comparator contains an input differential cascade

1, intermediate differential cascade 2 performed on transistors 3 and 4, the first level shift circuit 9 and the output key stage 12. The goal is achieved by introducing a current generator 5, the first 6 and second 7 voltage repeaters, an additional amplifier stage 8, the second level shifting circuit 10 , current repeater 11. The use of cascade 8 on transistors with a common base allows you to provide the best frequency properties of cascade 2 and the comparator as a whole, which improves speed. The device according to claim 2 of the formula is distinguished by switching between the outputs of the first 6 and second 7 voltage followers and the bases of the second 3 and first 4 transistors of the intermediate differential stage 2 of the first and second resistors, respectively. 1 hp f-ly, 1 ill.

The invention relates to radio engineering and is intended for use in analog-to-digital converters with high resolution.

The purpose of the invention is to increase the gain and speed.

The drawing shows an electrical schematic diagram of the comparator.

The comparator contains an input differential stage 1, an intermediate differential stage 2 performed on transistors 3 and 4, a current generator 5, the first 6 and second 7 voltage followers, an additional amplifier stage 8, the first 9 and second 10 level shift circuits, a current follower 11 and the output key stage 12.

The comparator works as follows.

Suppose that between the inputs of the input differential stage 1, the source of the differential signal is connected to the positive terminal to the upper one of the comparator input terminal. In this case, the differential voltage applied to the inputs of the intermediate differential stage 2 is 2 Δυ. Suppose that this voltage is small compared with the linear portion of the transfer characteristic of the intermediate differential stage 2. Then the collector currents of transistors 3 and 4 change accordingly by

+ Δυ ·

1679615 A1

3

1679615

four

-Δυ · ς

L! „C ° -e ^κτ

where Ιο is the initial bias current of the transistors 3 and 4, set by the current generator 5;

η is the electron charge;

K is the Boltzmann constant;

T is the absolute temperature.

Since the initial bias currents of the additional amplifiers of the 8-stage transistors are also equal! _0/2 , then the change in voltage at the inputs of this cascade, provided that its transistors are made of the same semiconductor material as transistors 3, 4, will be

_Lee , _x , = - ^ d, ^ =

H Ιο

+ Dcd

-KT = [n (e kt) ₌ _d _and: tc _x ^CH 2 = - { "=

H 1o

= - ^ ξ- ^{| πι} (θ ^к ') = + Δυ.

Voltage repeaters 6 and 7 transmit these voltage increments again to the bases of transistors 3 and 4. At the indicated polarity of the differential signal at the comparator input, the voltage increment at the base of transistor 3 was + Lee, the output of the first voltage follower 6 also receives + Δand. Similarly, the input signal at the base of transistor 4 is equal to - Δυ, and from the output of the second voltage follower 7 also comes - Δ and. The obtained voltage phasing ± Δυ and their value indicate that the intermediate cascade 2 of the comparator is covered by 100% positive feedback voltage at the transmission coefficient in the loop, approximately equal to one. Hence, the resulting conversion factor of the input differential voltage into output current from the inputs of the comparator to the collectors of transistors 3 and 4 is equal to

3ι-5g _ 3ι -5g _

1 ^- K4 _o ") 3 pos 1 - 1

where 5ι, Zg is the low-signal slope of the input differential stage 1 and intermediate differential stage 2 on transistors 3 and 4.

It is realistic, however, that the transmission coefficient in the PIC loop is always less than one (for example, because the voltage transfer coefficient of voltage followers 6 and 7 is always less than one, etc.). Therefore, the gain of the proposed comparator always has a finite value, by one or two orders of magnitude

5 higher than the gain at open PIC.

Since as for the PIC circuit current sensors used in the proposed comparator base-emitter junction of transistor 10, an additional amplifier stage 8, with the output of this stage it is possible to remove antiphase voltage and _YOU + Δ x, - Δi _B's. proportional to the collector currents of 15 transistors 3 and 4. The use of an additional amplifier stage 8 on transistors with a common base allows you to simultaneously provide the best frequency properties of intermediate differential stage 2 and the comparator as a whole, which positively affects its speed.

In contrast to the known comparators, the summation of the output currents of the additional amplifying cascade 8 in the proposed comparator is performed after shifting the level of these signals, which is carried out symmetrically using level circuits 9 and 10, directly

30 on the basis of the transistor output of the key stage 12. In this case, the transition to a single-phase signal is carried out using a current follower 11. The use of such a scheme does not affect the comparator parameters

35 in small signal mode. However, in this case, the base circuit of the transistor of the output key stage 12 is controlled by a symmetrical push pull signal, which makes it possible to significantly improve the symmetry of the temporal characteristics of the pulse drops at the comparator output in both directions. At the same time, the high broadbanding provided by the intermediate differential cascade 2 with the inner 45 of the POS and the additional amplifying cascade 8 together with the method used for controlling the transistor of the output key cascade 12 allows for a high response speed of the predicted comparator.

Limiting voltage drops to

the base of the transistor output key stage 12 can be carried out using conventional diodes or Schottky diodes (see

55 drawing). In the first case, additional resistors should be connected between the output of each shear circuit and the terminals of the current follower 11, to the upper terminals of which should be connected the anodes of current-limiting diodes.

five

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6

Ordinary zener diodes can be used as level shift chains 9 and 10. However, the best frequency-amplifying characteristics of the comparator are provided when using shear circuits with emitter followers (see drawing). In this case, to limit the current supplied to the input and output of the current follower 11, an additional emitter follower can be used in the circuit, the input of which is connected to a resistor that summarizes the currents of both level shifts 9 and 10, and the output is connected to the additional amplifier power bus cascade 8.

Claims (2)

Claim 1. A comparator containing an input differential stage, the outputs of which are connected to the bases of the first and second transistors of the intermediate differential stage, respectively, and the output key stage performed on a transistor connected to the common emitter circuit, and the first level shift circuit, one output of which is connected to the input of the output key stage, characterized in that, in order to increase the gain and speed, the first and second voltage followers, an additional amplifier, are introduced into it the first cascade made on the first and second transistors connected according to a common base circuit, a current repeater and a second level shift circuit, while the inputs of the first and second voltage followers are connected to the first and second inputs of the additional amplifier stage and with the collectors of the first and second transistors intermediate differential stage, respectively, and the outputs of the first and second voltage followers are connected to the bases of the second and first transistors of the intermediate differential stage, respectively, and The first output of the additional amplifier stage is connected to the second output of the first level shift circuit, and the second output through the second level shift circuit to the current repeater input, the output of which is connected to the input of the output key stage, and its common output is connected to the common bus. 2. Comparator pop. 1, characterized in that between the outputs of the first and second voltage followers and the bases of the second and first transistors of the intermediate differential stage are the first and second resistors, respectively.