SU1675903A1 - Device to define the arithmetic mean creeping - Google Patents

Abstract

The invention relates to specialized digital computing devices for determining the arithmetic average as applied to digital dynamic analysis systems and can be used in solving problems of approximation, signal smoothing, changes in the dynamic and frequency characteristics of samples in acoustics, location, communications, medicine, biology, in emergency systems. nuclear energy control. The aim of the invention is to enhance the functionality of the device by calculating a sliding three-point average of even and odd values. It is achieved by introducing into the device four registers, two averaging blocks, twelve AND elements, three adders, a NOT element, and two OR elements. The greatest effect from the use of the invention is achieved when it is used in systems of digital dynamic spectral analysis of signals in a sliding processing mode. High performance allows it to be included in the monitoring, tracking, and control equipment operating in real-time conditions. The device is designed for two stages of signal smoothing. 1 hp f-ly, 4 ill.

Description

The invention relates to specialized digital computing techniques for determining the arithmetic average as applied to digital dynamic analysis systems and can be used in smoothing digital signals in the areas of acoustics, seismology, sonar, medicine, biology, communications, and diagnostic systems for nuclear power plants.

The aim of the invention is the expansion of functional capabilities due to the possibility of calculating a sliding three-point average of even and odd values.

The device is designed to calculate a moving average of arithmetic numerical sequences based on a three-point averaging algorithm with the possibility of obtaining smooth digital sequences with respect to even and odd values from the numbers of discrete values of the input signal. The device allows, by smoothing the digital sequences, to influence the frequency characteristics of the processed signals, for example, prior to their spectral analysis, to eliminate unwanted peaks in the digital signals, to smooth out the bounce of the envelope of the digital signal.

ABOUT

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Fig, 1 shows a functional diagram of the device; Fig 2 is a diagram of the averaging block; in fig. 3 is a block diagram of operations in the averaging block; in fig. 4 - time diagram of the device.

The device (Fig. 1) contains registers 1-4, averaging blocks 5 and 6, triggers 7 and 8, elements AND 9-18, elements OR 19 and 20, a gate input 21, information input 22 and outputs 23 and 24.

The averaging unit (Figs. 2) contains adders 25-27, elements AND 28-33, element NOT 34, elements OR 35 and 36, inputs 37 and 38 of the block, and output 39 of the block.

The device works as follows.

The current discrete values Xi (i), where i is the value number, starting from one, t is the time, arrive at the inputs of registers 1 and 2 and the input of element 15, depending on the gating of registers 1 and 2 from elements 12 and 11, respectively. the odd X2i-i (t) values can be written either in register 1 or in register 2, and also transmitted to the output 23 of the first smoothing stage, i.e. at the output of the element OR 19.

The whole device has two stages of smoothing at even and odd values and, accordingly, two outputs 23 and 24. In the second stage of smoothing, the signal processed for the first time undergoes repeated smoothing (Fig. 4).

Using the averaging block 5, the smoothing mode of even values X2i (t) is organized over the neighboring odd values X4i-3 (t) and X / ii-i (t) when I is measured relative to the sync pulses C (Fig. 4),

At the output of the element OR 19, either the true odd values of X2i-i (t) through the element 15, or the smoothed even values of Xai (t) through the element 16 are fed.

In the second stage, odd values of X2i + i (t) are smoothed over adjacent even values. At the same time, registers 3 and 4 record the values of X4i-2 (t) and X4i (t), respectively (FIG. 4), on the basis of which the enblock 6 the smoothed x2H-1 value is calculated. Through elements AND 17 and 18 and OR 20, the data is transmitted to the second output 24 of the device. The essence of the work of the second stage is similar to the work of the first stage.

The device is controlled as follows.

Sync pulses C (Fig. 4) are fed to the counting input of the trigger 7. which, using the elements 9 and 10, breaks them into odd and even gates,

Using the trigger 8, the counting input of which receives an even sequence of gates, and elements 13 and 14 form a sequence of gates with numbers 4i-2 and 4 | relative to the sync pulses that are recorded in

registers 3 and 4.

On elements 12 and 11, gates with the numbers 4I-3 and 4i-i are formed, which are used to write data to registers 1 and 2.

0 The strobe from the output of the AND 9 element And 15 transmits all true odd values from the information input 22, The same strobe opens the element AND 18 for the passage of averaged odd values. The strobe from the output of the element And 10 opens the elements And 16 and 17 for the passage of the averaged even values.

Averaging unit 5 (fig. Is intended to calculate the average X2i (t) in the system

0 sliding signal smoothing using a three-point algorithm. It works as follows.

According to the data recorded in registers 1 and 2 with the help of adder 25,

5 comparison of X2i-i (t) and Xai + i (t). If Xan-ift) X2i-i (t), then, in accordance with the state of the first output of the And 29 element controlling the And 30 and 31 elements, the And 30 and 35 elements of the X2i-n (t) arrive

0 to input A, and the values of X2i-i (t) through AND 33 and OR 36 elements to input B of the second adder 26. For X2i-n (t) X2i-i (t) - vice versa: X2i-i (t) through elements AND 31 and OR 35 enters input A, a X2i + i (t) through elements AND 32 and OR

5 36 - to the input of the adder 26.

The element 28 is used to determine the summation attribute Z: if X2i-i (t) and X2n-i (v) have different signs — a sign of addition; otherwise, a sign of subtraction, which is

0 is applied to the functional inputs of the adder 26. Through these operations, HmaxM and HminM are determined.

Ultimately, a number is computed in adder 26, Q abs {XM3Kc (t) - XMinM / 2}

5 (the sign is ignored), which is then subtracted from Hmax (1) in adder 27. The output 39 of the adder 27 is formed average

Arithmetic Xcp (t) XMaicc (t) - Q, i.e. X2i (t) X2i ± i (t) -Q.

Block 6 operates and is gated like block 5,

FIG. 3 is a flowchart of operations during the operation of the averaging unit. FIG. 4 left numbers

5 denotes blocks in FIG. one.

If necessary, the device can be expanded by connecting similar smoothing sections with averaging schemes. The external processor can read data from

any of the outputs 23 or 24. When the device is executed on high-speed elements, it is possible to perform calculations with the time interval between the data up to 5 ns.

Claims (2)

An apparatus for determining a moving arithmetic average containing two flip-flops, four AND elements and the first OR element, the direct output of the first flip-flop connected to the first input of the first And element, the direct output of the second flip-flop the second input of which is connected to the output of the third element I, the first input of which is connected to the construction-input device, characterized in that, with the aim of extending the functionality by calculating a sliding valve It contains even, odd and even numbers, it contains the fifth, sixth, seventh, eighth, ninth and tenth elements AND, the second element OR, four registers and two averaging units, with the gate input of the device connected to the second input of the first element AND and the synchronous input the first trigger, the inverse output of which is connected to the information input of the first trigger and the second input of the third element I, the output of which is connected to the synchronous input of the second trigger and the first inputs of the fourth, fifth and sixth elements And, the output of the first The element I is connected to the first inputs of the seventh, eighth, ninth and tenth elements of the AND, the second input of the fourth element I is connected to the second input of the eighth element I, the information input of the second trigger and the inverse output of the second trigger, the direct output of which is connected to the second input of the seventh And, the outputs of the second and fourth elements And are connected to the inputs of the recording resolution of the first and second registers, respectively, the information inputs of which are connected to the second input of the sixth element And, the output of the first element LEE and are the first output device, an information input of which is connected to the data inputs of the third and fourth registers and the second input of a ninth AND gate, whose output is connected to a first input of the first element OR, the second input of which is connected to the output of the fifth element AND, the second input of which is connected to the output of the first averaging unit, the first and second inputs of which are connected to the outputs of the third and fourth registers, the recording resolution inputs of which are connected respectively to the outputs of the eighth and seventh elements And, outputs of the first and second registers connected to the first and second inputs of the second averaging unit, the output of which is connected to the second input of the tenth element AND, the output of which is connected to the first input of the second element OR, the second input of which is connected to the output of the sixth element And, the output of the second element OR is the second output of the device . 2. Device pop. 1, characterized in that the averaging unit contains three an adder, six AND elements, two OR elements and an NOT element, with the first input of the block connected to the first information input of the first adder and the first inputs of the first and second AND elements, the second the input of the block is connected to the second information input of the first adder and the first inputs of the third and fourth elements And, the second inputs of the first and third, second and fourth elements And are connected respectively to the direct and inverse outputs of the sixth element And, the first and second inputs of which are connected to the output of refraction the first adder and the output of the NOT element, whose input is connected to the output of the first adder, the outputs of the first and third elements AND are connected to the first and second inputs of the first OR element, the output of which a first data input the second and third adders, the outputs of the second and fourth elements And are connected to the first and second inputs of the second element OR, the output of which is connected to the second information input of the second adder, the first and second sign bits of which are connected to the inverse and direct outputs of the sixth element And, the first and the second inputs of which are connected with the sign bits of the first and second inputs unit, the output of which is connected to the output of the third adder, the second information input of which is connected to the output of the second adder. and V t IT P1 s  ELUAG X eo6si9i