SU1660188A1 - Adaptive device for noise suppression in voice signals - Google Patents

Abstract

This invention relates to radio engineering and can be used to increase the intelligibility of a noisy speech signal. The aim of the invention is to improve the noise immunity of a speech signal by improving the signal-to-noise ratio. The device contains an on-line storage unit 1, a permanent storage unit 2, a multiplier 3, an adder 4, a function calculation unit 5, buffer registers 6-13, multiplexers 14-17, a control unit 18. The device allows for the suppression of noises that are continuous in time and are in the spectrum of the received speech signal. 2 Il.

Description

31СЧ

Address | | C5poc

bull

v

yo

LTD

with

00

This invention relates to radio engineering and can be used to increase the intelligibility of a noisy speech signal.

The aim of the invention is to improve the noise immunity of a speech signal by improving the signal-to-noise ratio.

FIG. 1 shows a block diagram of the device; in fig. 2 is a block diagram of the control unit.

The device (Fig. 1) contains an operational storage unit (OZB) 1, a permanent storage unit 2 (PZB), a multiplier 3, an adder 4, a function calculation unit 5, first 6, second 7, third 8, fourth 9, fifth 5 , sixth 11, seventh 12 and eighth 13 buffer registers, first 14, second 15, third 16 and fourth 17 multiplexers, control unit 18, device input 19, device output 20.

The control unit 18 (Fig. 2) contains a clock frequency generator 21, a counter 22, a start signal generation unit 23, a permanent memory unit 24.

The device works as follows.

Function calculation block 5

p (xg) (Fig. 2) is made on a multiplexer, with the first information input of the multiplexer receiving information from the output of the fifth buffer register 10, the second information input is a constant value Ci, the third information input is a constant value C2, the control inputs of the multiplexer receive an overflow signal and a sign bit from the fifth buffer register 10. /.

A constant value is applied to the third input of the second multiplexer 15.

At the input of the device 19, a noisy speech signal Zt + ъ is received and at the output 20 a speech signal xt + r1 is obtained with an improved signal-to-noise ratio. The procedure for processing a noisy speech signal is described by the following equations:

{W (+ i j-vtM

u-,

m

J

} til () X t Xt

,,

,five

“Ј ,, .z.

ttt, -u (2 t x t -xt

. f "l

. ., i +, With -U Х6 |;

H (x, b | C, "-0.024 at x" H .024 at x

where K (1) is the gain for estimating the first reference signal xt;

K (2) is the gain for estimating the second sample of the signal xt – i; K (3) is the gain for estimating the excitation function;

K (4) is the gain for estimating the first linear prediction coefficient;

K (5) is the gain for estimating the second linear prediction coefficient; l (i) xt-nv output signal; x1 + 1 is the first

linear prediction ratio.

xt + r5 is the second linear prediction coefficient.

It was established experimentally that as initial conditions it is advisable to take the following values

x0 (0; ho (4) 0.8; x0 ® 0.4.

The values of K (1), K (2), K (3), K (4), K (5) are constant during the calculation process and are selected experimentally in the range of 0.05-0.25 depending on the power signal interference acting on the input. The value of Ј is constant, experimentally chosen Ј -5 10 2.

The process of calculating the signal xt + 1 consists of 21 cycles, which proceed as follows.

During the 1st cycle (Fig. 3), the value xY1 is read from OZB 1 and

writing it through the first multiplexer 14, which is in the 1st state, to the first buffer register 6.

During the 2nd clock cycle of their HBD 1, the value xr1 is read out and, via the second multiplexer 15, which is in the 1st state, is written to the second buffer register 7.

During the 3rd cycle, the multiplication of xt / xt by multiplier 3 is performed, the first and second inputs of which, respectively, from the first and second buffer registers 6 and 7 receive the values xv and xg and the result of the multiplication is written to the sixth buffer register 11. Also

during the 3rd cycle, their OZB value xy is read and written to the buffer register 10.

During the 4th cycle, the value is read from the OZB and recorded in

the first multiplexer 14, which is in the 1st state, into the first buffer register 6. Also during the 4th clock cycle,

. L ft) h

calculating the value of p (Xt g. When “(3) value of the number xf is found within

l (h)

-1 Xf 1 its numerical value, coming from the fifth buffer register 10 through block 5, goes to the second pass of the first multiplexer 14. When the value of the number xY3 in area 1 is block 5 under the action of control signals from the fifth buffer register 10, and it is the sign of the number and bit of overflow that switches to the second state, skipping to its output a constant number Ci 0.024. When finding the value of the number x / in the area xf -1 block 5 under the influence of the control signals from the fifth buffer register 10 switches to the third state, the value Ci 0.024 passes to its output.

During the 5th clock cycle, the xt® value is read from OZB 1 and written through the second multiplexer 15, which is in the 1st state, to the second buffer register 7.

During the 6th cycle, the multiplication of xt values is performed. xt, arriving at the 1st and 2nd inputs of the multiplier 3 from the first 6 and second 7 buffer registers. The result of the multiplication is written to the seventh buffer register 12.

During the 7th cycle, the summation is performed 2) xWxK + by adder 4, for

eleven

what its 1st and 2nd inputs get the values of x / xt and xY2W through the third and fourth multiplexers 16 and 17, located in the 1st position of the sixth 11th and seventh buffer registers. The result of the sum is written to the third buffer register 8. Also in the 7th cycle,

writing the value of p (xyy) to the first buffer register 6 via the first multiplexer 14, switching in this state to the 2nd state, and writing the value Ј to the second buffer register 7 through the second multiplexer 15, being in the 2nd state. During the 8th cycle, the value of Zt + 4-2x is calculated (Ox (l + for what on the 1st

| input of adder 4 is supplied the value

Y xk x 9 of the third buffer register

8 through the third multiplexer 16, switched in the 8th cycle to the 3rd state, and the 2nd input of the adder 4 receives the input value Zt + 1 through the fourth multiplexer 17, switched in this cycle to the 2nd state. The result of the sum is written to the fourth buffer register 9. In addition, multiplication (xH) is performed in the 8th cycle. for what the 1st and 2nd entrances

multiplier 3 is supplied respectively

the p (xf) and величины values from the first 6 and second 7 buffer registers, and the result of the multiplication is recorded in the sixth 5 buffer register 11.

During the 9th cycle, the transfer of the value of Zt + t -Y хЬ1 $ to 9 from even 1 is performed.

Q of the correct buffer register 9 to the eighth buffer register 13.

During the 10th clock cycle, the value is calculated, for which the 1st input of the adder 4 through the third multiplexer 16, which is 5 s in the 2nd state, the xV3 value from the fifth buffer register 10 enters. and the 2nd input of the adder 4 receives the value of Zt + G

- xK xT from the eighth buffer reg - (

0 country 13 through the fourth multiplexer 17, which is in the 3rd state. The result of the sum is written through the second multiplexer 15. in the 3rd state, to the second buffer register 7. Also

5, the 10th cycle reads from

 PZB 2 values of K (1) and write it through

the first multiplexer 14 located in

3rd state, in the first buffer register

6

0 in the 11th cycle multiplication K (1) t + i is performed, for which the th input of multiplier 3 from the first buffer register 6 receives the value K (1), and the 2nd input

to multiplier 3 of the second buffer pe (z

Gist 1 receives the value of Vt-m. The result of the multiplication is written to the seventh buffer register 12.

In the 12th cycle, the summation K (1) vt + i is performed, for which, the 1st input of the adder 4 through the third multiplexer 16, which is in the 2nd state, receives the value xY3 from the fifth buffer register 10 and the 2nd input of the adder 4 through the fourth multiplexer 17, which is in the 1st state, receives the value K (1) from the seventh buffer register 12. The result of the summation is written into the fourth buffer register 9. Also in 12 -th cycle reads K (2) from PZB 2 and writes it through the first multiplexer 14, which is in the 3rd state, in the first buffer ny register 6.

In a 13-second cycle, the value of xt® + K (1) VtTi is transferred from the 4th buffer register 9 to the eighth buffer register 13,

multiplication of K (2) vt t 1 by a multiplier of 3, for which its first input from the first

five

0

the buffer register 6 receives the value K (2); the second input from the second buffer register 7 receives the value and the result of the multiplication is written into the seventh buffer register 12. Also in the 13th cycle, the XY value is read and its write to the fifth buffer register 10.

In the 14th cycle, the calculation of xt + 1, which is the output value, is performed, for which the first input of the adder 4 through the third multiplexer 16, which is in the 3rd state, receives the value of

5) xb) x (-, and on the 2nd entrance through the fourth

multiplexer 17, in the third state, the value xY3 + K (1) vt-mis of the eighth buffer register 13. The result of the summation is recorded in OZB 1. Also in the 14th clock cycle, the values of K (3) and writing it to the first buffer register b through the first multiplexer 14, which is in the 3rd state.

In the 15th cycle, the value of xt + 1 is calculated, for which the 1st input of the adder 4 receives the value x + 1 from the fifth buffer register 10 through the third multiplexer 16, which is in the 2nd position, and at 2 The input of the adder 4 receives the value K (2) from the seventh buffer register 12 via the fourth multiplexer 17, which is in the 1st position. The result of the summation is recorded in AHB 1.

In the 16th cycle, multiplication K (3) ffҐi is performed by multiplier 3, for which the 1st input of multiplier 3 from the first buffer register 6 receives the value K (3), and the 2nd input of multiplier 3 is the value from the second buffer register 7. The result of the multiplication is written to the seventh buffer register 12,

In the 17th cycle, the value of r is calculated, for which the 1st input of the adder 4 via the third multiplexer 16, which is in the 1st state, from the sixth buffer register

11 enters the value Ј p (xH /), and to the second input of the adder 4 through the fourth multiplexer 17, which is in the 1st position, from the seventh buffer register 12

the value of K (3) is received. The result of the summation is written to OZB 1. Also, in the 17th cycle, the readout of the PZB 2 of the K (4) value and its writing through the first multiplexer 14, which is in the 3rd position, is written to the first buffer register 6 .

In the 18th cycle, the K (4) VHM multiplication by multiplier 3 is also performed, for which the AL input is transferred to the 1st input of the multiplier 3 from the first buffer register 6

To (4), and on the 2nd entry the value of ui from the second

buffer register 7. The result of the multiplication is recorded in the seventh buffer register 12. Also in the 18th cycle, the

reading xt from OZB 1 and writing it to the fifth buffer register 10.

In the 19th cycle, the value of xt + 1 is calculated, for which the 1st input of the adder 4 receives the value through the third multiplexer

16, in the 2nd state, out of the p buffer register 10, and on the 2nd entry

adder 4 receives the value of K (4). through the fourth multiplexer 17, which is in the 1st state, from the seventh buffer register 12, the result of the summation is recorded in the AHD 1. Also in the 19th clock cycle, the 2 K (5) reads and writes it to the first buffer register 6 through the first multiplexer 14 located

in the 3rd state,

In the 20th cycle, the multiplication K (5) Vt + i is performed by multiplier 3, for which the 1st input of the multiplier 3 receives the value K (5) from the first buffer register

6, and the 2nd input receives the value m4 + 1 from the second buffer register 7. The result of the multiplication is recorded in the seventh buffer register 12. Also in the 20th cycle

reads the value xY5 from OZB 1 and writes it to the fifth buffer register 10.

In the 21st cycle, the value of xt + 1 is calculated, for which the 1st input of the adder 4 receives the value through the third multiplexer 16, which is in the 2nd state, out of the fifth buffer register 10, and on the 2nd the input of the adder 4 enters the value through the fourth multiplexer

17. being in the 1st state, from the seventh buffer register 12. The result of the summation is recorded in the SAR 1.

The control unit 18 (FIG. 2) operates as follows.

When the power is turned on, the start-up generation unit 23 generates a Start-up signal, which resets the counter 22 and the PSA (Fig. 1) to the initial state. The counter 22, under the influence of pulses, arrives from the generator 21. forms the address for the fixed memory unit 24, in which the device control microcommands are recorded for each clock cycle.

Claims (1)

Invention Formula An adaptive noise cancellation device in a speech signal containing a multiplier, the first and second inputs of which are connected to the output of the first and second buffer registers, respectively, the adder, whose output is connected to the inputs of the third and fourth buffer registers, the persistent storage unit and the control unit, the first The second, third, fourth, and fifth outputs of which are connected respectively to the control inputs of the first, second, and third buffer registers, as well as to the address inputs of the permanent storage unit, Fifth, sixth, seventh and eighth buffer registers, which are designed so as to increase the noise immunity of the speech signal by increasing the signal-to-noise ratio, the operational storage unit, the function calculation unit, the first, second, second, third, and fourth multiplexers, the outputs of which are connected respectively to the information inputs of the first and second buffer registers, the first and second inputs of the adder, the output of which is connected to the information input of the operational storage unit, the first input of the second multi plexer and is the output of the device, the input of which is 27 Pogo is the first input of the fourth multiplexer, the second and third inputs of which are connected respectively to the outputs of the seventh and eighth buffer registers, whose information input is connected to the output of the fourth buffer register, and the output of the operational storage unit is connected to the first input of the first multiplexer, the second input of the second multiplexer and the information input of the fifth buffer register, the first and second outputs of which are connected to the corresponding inputs of the function calculator and the first input third multiplexer, The second and third inputs of which are connected respectively to the outputs of the third and six-buffer registers, whose information input is combined with the corresponding input of the seventh buffer register and connected to the multiplier output, the output of the function calculator connected to the second input of the first multiplexer, the third input of which is connected to the constant output memory block, and the control inputs of the first, second, third, and fourth multiplexers, the fifth, sixth, seventh, and eighth buffer registers, the address and control inputs of the operational storage unit connected to the corresponding outputs of the control unit. 22