SU1658392A1 - Device for radio pulse interference suppression - Google Patents

Abstract

The invention relates to radio engineering and can be used as part of receiving devices of radar signals with intrapulse modulation of frequency or phase according to a well-known law. The RFI suppression device contains delay elements 1.29, 33, and 34, subtractor 2, frequency and phase adjustable oscillator 3, keys 4, 15, 22, and 24. quadratic detector 5, threshold elements 6 and 10, coincidence element 7, limiter 8, matched filter 9, expander 11 and 28 pulses, inverter 12, synchronous detector 13, amplifier-limiter 14, adders 16, 21 and 32, integrator 17, multipliers 18 and 30, phase shifters 19 and 31, amplitude detector 20, comparator 23 , a 25-character detector, a D-trigger 26, a signal detector 27 and a controllable integration op yl 35 3 (/ C

Description

The invention relates to radio engineering and can be used as part of radio receivers of radar signals with intrapulse frequency or phase modulation according to a known law.

The purpose of the invention is to increase the ratio of the power of the useful signal to the power of the radio pulse interference, characterized by rare changes in the level of the envelope inside the radio pulse or from pulse to pulse. _t

In FIG. 1 is a structural electrical diagram of a device for suppressing radio pulse interference; in FIG. 2 and 3 stress diagrams explaining the operation of the device.

The device for suppressing radio pulse interference includes a first delay element 1, a subtractor 2, a frequency and phase adjustable generator 3, a first key 4, a quadratic detector 5, a second threshold element 6, a coincidence element 7, a limiter 8, a matched filter 9, a first threshold element 10, first pulse extender 11, inverter 12, synchronous detector 13, limiter amplifier 14, second switch 15, first adder 16, integrator 17, first multiplier 18, first phase shifter 19, amplitude detector 20, second adder 21, fourth switch 22, computer ator 23, third key 24, sign detector 25, D-flip-flop 26, signal detector 27, second pulse expander 28, second delay element 29, second multiplier 30, second phase shifter 31. third adder 32, third delay element 33, fourth element 34 delays and managed integrator 35.

A device for suppressing powerful radio pulse interference works as follows.

Let an additive mixture of the useful signal, noise “uncorrelated with it” and noise arrive at the input of the device. The signal is an amplitude ohm nor a pulsed sequence of radio pulses of duration T _s with intrapulse modulation in frequency and (or) phase. The interference is a radio pulse of duration T _n with a constant carrier frequency, or a radio pulse with intrapulse modulation in frequency and (or) phase, or a quasi-harmonic oscillation modulated in amplitude and phase (frequency) according to a random law. It is assumed that noises do not trigger a detector of a powerful process (blocks 5 and 6), therefore, they do not affect the operating principle of the device and are not taken into account in the further discussion. Signal and interference parameters: time delay, amplitude (power), initial phase are assumed to be unknown (random) values.

The input process is delayed by the first delay element 1 for a time T ₃ and is fed to the input of the first subtracter 2. At the same time, the delayed signal is fed to the input of a frequency and phase-adjustable oscillator 3, which generates a constant amplitude oscillation with a frequency and phase that approximately coincide with the frequency and phase of the interference . Uncompensated residual noise from the output of the first subtractor 2 is fed to a synchronous detector 13, the output signal of which through the first adder 16 is fed to the input of the integrator 17 and then to the input of the first multiplier 18. At the same time, to another input of the synchronous detector 13 and another input of the first multiplier 18 through the closed first switch 4 receives oscillation from the output of the frequency and phase generator 3. As a result, a high-frequency compensating voltage is generated at the output of the first multiplier 18, which, through the first phase shifter 19 is fed to another input of the first subtractor 2. If the amplitude of the compensating voltage is greater than the amplitude of the interference at the output of the first delay element 1, then the error voltage at the output of the synchronous detector 13 is negative, which leads to a decrease in the voltage at the output of the integrator 17 and, accordingly, amplitudes of compensating voltage. If the amplitude of the compensating voltage is less than the amplitude of the interference, then the sign of the error voltage at the output of the synchronous detector 13 is positive, which causes an increase in the voltage at the output of the integrator 17 and, therefore, the amplitude of the compensating voltage. Thus, the device equalizes the amplitudes of the compensating voltage and the interference at the inputs of the first subtracter 2. In this case, the integrator transmission coefficient and loop gain in the correlation feedback circuit are chosen such that the speed of the adjustment circuit of the amplitude of the compensating voltage is at least higher than the maximum envelope change rate interfering vibration.

Consider the operation of the device in various signal-noise situations, namely: 1) when exposed to a useful signal overlapping in time and powerful interference: 2) when exposed to a useful signal of a large level.

Let the additive mixture of the useful signal and powerful radio-pulse interference (Fig. 2, a) be supplied to the input of the device. The hatching conventionally indicates the occurrence of beats in areas where the signal and noise overlap in time. At the output of element 1, this voltage is repeated almost without distortion with a time delay of T ₃ (Fig. 2.6). After being detected by quadratic detector 5, the voltage is compared with the Unop threshold. in the second threshold element 6 (Fig. 2.B). While the voltage at the output of the quadratic detector 5 is less than Unop (time interval t ₀ -ti of Fig. 2, c), the first switch 4 is open, at the corresponding inputs of the first and second multipliers 18 and 30 and the synchronous detector 13 the zero potential is set, there are no oscillations at the outputs of the first and second phase shifters 19 and 31 and the input action without distortion with a constant delay in the first and third delay elements 1 and 33 is transmitted to the output of the device. The zero potential in the time interval t _o -ti is also supported at the output of the first adder 16, which ensures that the output of the integrator 17 is of a constant level, formed at the time the compensation process for the previous interference pulse is completed. As will be understood from the further description of the operation of the device, at the moment of closure of the first switch 4 when a powerful pulse noise arrives, the output voltage of the integrator 17, and hence the level of the compensating voltage at the output of the first phase shifter 19, does not depend on the amplitude of the previous interference pulse and differs from Unop less than the value of the reference voltage U _o . Therefore, with an increase in the output voltage of the quadratic detector 5 to a value of Unop. at time ti, i.e. when the coincidence element 7 generates a rectangular strobe pulse and the voltage from the output of the frequency and phase adjustable oscillator 3, due to the closure of the first switch 4, is supplied to the first subtractor 2 through the corresponding control circuits, an abrupt level change is observed at the output of the KOS loop to a value AU ₀ less than Uo (Fig. 2, h). The voltage from the output of the frequency and phase-adjustable generator 3 is simultaneously supplied to the input of the synchronous detector 13, while the integrator 17 exit! mode and starts storing nakopp ^g of error signal with you progress synchronous detector 13. i.e. from time ti, the device operates in the mode of interference compensation with a slow change in the level of the envelope. Note that at the output of the comparator 23, a low logic level is maintained all this time, since 1) in the time interval t ₀ -ti, the third key 22 is open, at the signal input of the comparator there is a zero potential, which. Naturally, it is less than the reference level U _o : 2) at the time ti, the third switch 22 closes, however, a voltage Δυ ₀ appears at the signal input of the comparator 23. equal to the amplitude of the output voltage of the KOS loop. which is less than U _o . Accordingly, the fourth switch 24 is open, its output has zero potential, the voltage at the output of the second adder 21. And, therefore, at the signal input of the comparator 23 is equal to the amplitude of the output voltage of the first subtractor 2. The second switch 15 is also open, the voltage at the input of the integrator 17 is equal to the output voltage synchronous detector 13. i.e. fast adaptation circuits (blocks 14, 15, 20 - 24) do not affect the process of interference compensation.

Starting from the moment ti, the voltage at the output of the KOS loop quickly increases in accordance with the steepness of the front of the interference pulse that came to the input of the device, which, due to the inertia of the KOS loop, is transmitted almost without change to the output of the first subtractor 2.

When the uncompensated residuals exceed the interference at the output of the CBS loop of the Uo level, the quick adaptation mode is activated. At the output of the comparator 23, a high logic level appears (Fig. 2d), closing the second and fourth keys 15 and 24. As a result of the closure of the second key 15, an additional constant voltage is supplied to the input of the integrator 17 through the first adder 16 and _{up to} b from the output of the amplifier-limiter 14 (Fig. 2, d). Due to the fact that the sign of this voltage coincides with the sign of the error signal at the output of the synchronous detector 13, both of these voltages act in phase and therefore there is a sharp acceleration of the process of adaptation of the device to an abrupt change in the noise amplitude. The quick adaptation mode ends after the output voltage of the device becomes equal to zero. For this, the comparator 23 is clicked on with the voltage U _o transmitted through the fourth key 24 to the signal input of the comparator and, accordingly, a hysteretic on-off characteristic of the quick adaptation mode is provided: this mode is turned on when the voltage at the output of the amplitude detector 20 exceeds Uo. shutdown - when decreasing it to zero.

As a block 23, it is advisable to use a comparator with a zero zone, the width of which is equal to Ui. The inclusion of quick adaptation circuits in this case will occur when the voltage at the output of the first subtractor 2 exceeds the value Ui + U _o , and it turns off when it decreases to Ui. This significantly increases the reliability of the operation of the device, since it provides disconnection of quick adaptation circuits with incomplete compensation of interference due to hardware. errors, as well as the line of the useful signal at the output of the device. In this case, it is recommended to choose a value Ui slightly larger, and U _o 3-4 times higher than the maximum amplitude of the useful signal. In the following presentation, to emphasize the basic principles of the device and in order to simplify the diagrams, it is assumed that Ui = 0,

So, at time t ₂ , when the amplitude of the input signal reached U _o , the fast ”adaptation mode is turned on and, after time At ₂ (zXt _{2 is} much shorter than the rise time of the noise front), the voltage at the output of the CBS loop drops to zero. In this case, the fourth key 24 opens, and the device returns to the adaptation mode to slow fluctuations in the amplitude of the interference.

As a result of several on-off cycles of the quick adaptation mode, the device monitors a jump-like change in the amplitude of the interference with a dynamic error not exceeding U _o . After the end of the front of interference, the device goes into normal adaptation mode, the compensation error slowly decreases with the speed due to the speed of the KOS loop.

Suppose that at the time point gz (Fig. 2.c), along with a powerful noise, a useful signal of duration Tc is supplied to the input of the CBS loop. Up to this point, the fast adaptation mode control circuits are oriented only to sharp changes in the envelope of interference (since there are simply no signal ones yet), and therefore the useful signal detector 27 does not detect the presence of signal components at the output of Trigger 26, and a low logic logic level is maintained at the control input of the integrator 35 level, and at its output zero potential. The amplitude of the correction voltage at the output of the second phase shifter 31 is equal to zero and oscillations! from the output of the KOS loop through the third adder 32 s. an additional constant delay in the third element 33 without distortion are transmitted to the output of the device.

Consider the case when the amplitude of the useful signal exceeds the level of Uo. therefore, the appearance of a useful signal at the output of the CBS loop causes the inclusion of fast adaptation circuits; at the output of the CBS loop, partial or complete suppression of the components of the useful signal is observed (interval Xs - Xs + T _s , Fig. 2, h). As can be seen from FIG. 2e, the operation of the fast adaptation circuits in the interval xs - xs + T _s coincides with the arrival of the edges of the pulses of the useful signal, and in the case of the leading edge of the pulses, the voltage at the output of the second switch 15 is positive, and for the trailing edge is negative. We show that the use of information about the moments of switching on and off of fast adaptation circuits, while taking into account the polarity of the error signal of the CBS loop, allows us to restore the useful signal at the output of the device with the help of a special correction circuit.

So, in the time interval rz - t3 + T _s , when a useful signal is present at the input of the device, the control circuits of the fast adaptation mode of the KOS loop are oriented to the components of the useful signal and partially suppress them. In FIG. 3, and on an enlarged scale, diagrams of the signals at the output of the CBS loop for the described situation are shown, corresponding to FIG. 2, h, in FIG. 3.6 shows short pulses at the output of comparator 23, corresponding to FIG. 2d, in FIG. 3d corresponding to FIG. 2, d additional voltage at the output of the second switch 15, the supply of which provides a quick adjustment of the level of the compensating voltage to the amplitude of the input signal. The moment of capture by fast adaptation circuits is fixed by analysis circuits containing a sign detector 25, a D-trigger 26, and a signal detector 27. For this, the sign detector 25 determines the polarity of the compensation error signal at the output of the synchronous detector 13, which, as can be seen from FIG. 3c, it changes not only at the beginning and at the end of suppressed pulses (both interfering and signal), but also inside the interfering pulse over a time interval when the CBS loop tracks slow changes in the level of compensated interference. In FIG. C. the appearance of a positive constant voltage indicates an undercompensation of interfering oscillations and corresponds to a high logical level at the output of the sign detector 25, the appearance of a negative voltage indicates the operation of the KOS loop in the overcompensation mode, which corresponds to a low logical level at the output of block 25.

As can be seen from FIGS. 2, c, d, the leading edge of the signal pulses (however, as well as the noise) is characterized by a mode of undercompensation, and by the back - overcompensation. and abrupt changes in the compensating level when the quick adaptation mode is activated is usually caused by the beginning or end of an interfering (signal) impulse. Therefore, it can be argued that if at the moment the comparator 23 was turned on, the compensation error signal at the output of the synchronous detector 13 was positive, then the fast adaptation mode is activated due to the action of the leading edge of the compensated pulse, and if negative, the action of the falling edge. Based on this rule, it is possible to restore the structure of suppressed signals by setting the logic element (block 26) to a high logic level when determining the arrival of the leading edge of the suppressed pulse and low when fixing the trailing edge of this pulse. This operation is performed by a D-flip-flop 26, to the signal input of which voltage is supplied from the output of the sign detector 25, and to the synchronization input - from the output of the comparator 23. As a result, the output of the flip-flop 26 is observed only at the moment of operation of the fast adaptation circuits (Fig. 3 , e), and the level recorded at these times at the trigger output remains until the next pulse arrives from the output of the comparator 23, regardless of the change in the polarity of the error signal in the compensation interval for slow fluctuations of the interference amplitude. Thus, at the output of the D-flip-flop 26, a binary sequence is formed in which the changes in the logic level are synchronous with the fronts of both powerful interfering oscillations and weak signal pulses (Fig. 3e). The signal detector 27 detects the presence of orientation on the signal components in this sequence and forms a short standard pulse at the end of the analysis interval (for simplicity at the end of the pulse train of duration T _s ) (Fig. 3f), which indicates the capture and suppression of fast compensation circuits by the CBS loop useful signal. The second pulse expander 28 along the leading edge of the detection pulse forms a strobe of duration T _s (Fig. 3g), which puts the controlled integrator 35 into active mode. The parameters of the integrator 35 are identical to the parameters of the integrator 17 of the KOS loop and, therefore, throughout the strobe it generates a voltage that is a copy of the components of the output voltage of the integrator 17 delayed in the second element 34 resulting from the action of fast adaptation circuits. Here, the additional voltage from the output of the second switch 15 is delayed in the element 34 for a time equal to the analysis time in the signal detector 27 (in this case, on Tc, Fig. 3, h), and synchronously with the strobe pulse is supplied to the input of the integrator 35. As a result, its output forms a sequence of pulses (Fig. Z.i). repeating the envelope of the compensating voltage component of the KOS loop due to the action of fast adaptation circuits. After transferring this sequence of video pulses to a high frequency in the second multiplier 30, to the other input of which a carrier of the compensating voltage synchronously delayed in the element 29 is supplied, the correction voltage thus formed through the second phase shifter 32 is supplied to the input of the adder 32. It enters the other input of the adder synchronously with the correction voltage delayed in the third delay element 33, the signal from the output of the loop CBS (Fig. 3, l). As a result of the summation, the useful signal is completely restored (Fig. Z.i.) which is transmitted to the output of the device.

Thus, in the proposed device, a significant suppression of interference occurs without attenuation of the useful signal even when the level of the useful signal is higher than U _o and causes the operation of fast adaptation circuits. When a powerful useful signal is applied to the input of a device, the powerful process detection channel works the same way as in the case of powerful interference. A compressed pulse of large amplitude is formed at the output of the matched filter 9, since in this case the voltage at the output of the limiter 8 turns out to be strongly corrected with a useful signal. A compressed pulse with a delay Tc relative to the beginning of the arrival of the useful signal is supplied to the input of the first threshold element 10. fixing the moment of arrival of the useful signal. The pulse from the output of the element 10 is converted in the expander 11 into a pulse of duration T _s . is inverted by inverter 12 and arrives at the input of coincidence element 7, which locks the first key 4.

Thus, under the action of a useful signal of high power, the compensating and correcting voltages are zeroed, the useful signal passes through the first delay element 1, the first subtractor 2, the third delay element 33, and the third adder 32 without distortion. The constant delay in elements 1 and 33 is a systematic error in measuring the time of arrival of the signal and can be easily taken into account during further processing.

Claims (1)

Claim A device for suppressing radio pulse interference, comprising a series-connected limiter, a matched filter, a first threshold element, a first pulse expander, an inverter and a coincidence element, connected in series with a first delay element, the input of which is connected to the input of the limiter and is the device input, a quadratic detector and a second threshold element, the output of which is connected to another input of the match element, the first key whose control input is connected to the output of the match element is connected sequentially the first phase shifter, a subtracter, the other input of which is connected to the output of the first delay element, and a synchronous detector, connected in series with the first adder, the first input of which is connected to the output of the synchronous detector, an integrator and a first multiplier, the other input of which is connected to the other input of the synchronous detector in series limiting amplifier, the input of which is connected to the output of the synchronous detector, and the second switch, the output of which is connected to the second, the input of the first adder, are connected e sequentially an amplitude detector, the input of which is connected to the output of the subtractor, and a second adder, a third key, the output of which is connected to another input of the second adder, a comparator whose output is connected to the control inputs of the second and third keys, the signal input of the third key and the first input the comparator is the input of the constant reference voltage of the device, a frequency and phase tunable generator, the input of which is connected to the output of the first delay element, characterized in that, in order to increase the power ratio the useful signal to the power of the radio pulse interference, characterized by sharp changes in the level of the envelope inside the radio pulse or from pulse to pulse, and to reduce the distortion of the useful signal, a D-trigger connected in series is introduced, the synchronization input of which is connected to the output of the comparator, the signal detector and the second pulse expander , a sign detector, the input and output of which are connected respectively to the output of the synchronous detector and to the signal input of the D-trigger, connected in series to the second the delay element, the input of which is connected to the other input of the synchronous detector and to the output of the first key, the second multiplier, the second phase shifter and the third adder, the output of which is the output of the device, the third delay element, the input and output of which are connected respectively to the output of the subtractor and to the other input of the third an adder connected in series with a fourth delay element, the input of which is connected to the output of the second key, and a controlled integrator, the control input and output of which are connected respectively to the output the second pulse expander and with another input of the second multiplier, the fourth key, the input and output of which are connected respectively to the output of the second adder and the second input of the comparator, and the control input of the fourth key is connected to the output of the coincidence element, the input of the first key is connected to the output tunable in frequency and phase of the generator, the output of the first multiplier is connected to the input of the first phase shifter. 1 bi '0042 Figure 2 Figure 5