SU1647764A1 - Adaptive governor for reactive power compensators - Google Patents

Abstract

The invention relates to electrical engineering, in particular to devices that improve the quality of electricity. The purpose of the invention is to expand the functionality of the controller. The device can operate both in the mode of maintaining the voltage of the load node and in the mode of compensation of the power of the load. Signal comparator 7 provides on-off sections of capacitor banks by block 24 through one channel of forming control code combination on register 23 in accordance with counter 20 (in the first mode). Starting and stopping the generator 11 controls the comparator 10 depending on the signal level at its inputs from rectifier 5, analog switch 3, input signal from reactive power sensor 2 1) Output 5 and analog adder 6 and 8 bh, reference signal U0ni and feedback signal .18 chain-generated generator 11 — summing counter 13 — digital-to-analog converter 18. With IWs and outputs ip1, switch 10 starts generator 11 and stops it at a ratio of iy5 and iyb i0n1 + 1) output18. At the same time, the counter 13 is nullified, and the pulse of the single-vibrator 19 reads the code from the register 23, the capacitor battery sections are switched, ensuring that the voltage of the load node is maintained at which the output of Uon.1 and the circuit is decelerated. In the second mode, the switch 8 provides zeroing of the counter 20 and the same conditions of its operation with the counter 13, issuing the reference signal Uon.2 from the analog switch to the analog adder 6. Otherwise, the operation of the circuit is similar to that of the pheme in the first mode. 3 il. Ё ON N VI v | ABOUT

Description

The invention relates to power engineering and, in particular, to devices for compensating reactive power and improving power quality.

The purpose of the invention is to expand the functionality of the controller by changing its operating modes when adjusting the balance of reactive power or maintaining the voltage of the load node.

Figure 1 shows the block diagram of the adaptive regulator of the reactive power compensator; Figures 2 and 3 are timing diagrams explaining the principle of operation of the controller.

The adaptive controller contains a voltage deviation meter (ION) 1, a reactive power sensor 2 (FDM), 3-4 analog switches, a precision rectifier 5, an analog summation circuit 6, a comparator 7 for determining the sign of the signals, a program switch 8 modes (SPR ), the comparator 9 resets the summing counter, the comparator 10 starts the generator 11 pulses, the logical element 2 and 12, the summing counter 13, the logical elements ZI-NOT 14-16, the logical element NOT 17, the digital-to-analog converter (D / A) 18, the one-shot 19, the reversible binary A counter 20, a logic element 4 OR 21, a logic element 4I-NOT 22, a memory register 23, a block 24 for activating the capacitor sections.

The regulator works as follows.

In the maximum load mode of the power system, the compensator is used in the reactive power compensation function to reduce the total reactive power of the consumers.

In other modes, the reactive power compensator is used to maintain the voltage at the load connection nodes.

A signal proportional to the load current i (t) is fed to the second input of the HLR 2 (Fig. 1), to the first input of which and to the input of ION 1 a signal is received that is proportional to the voltage U (t) on the tires of the load node. At the output of ION-1, a signal is generated that is proportional to the deviation of the bus voltage from the optimal value, which is fed to the first input of the analog switch 3. At the output of the HDM 2, a signal is generated that is proportional to the reactive power consumed by the load, which is fed to the second input of the analog switch 3 ,

SPR 8 sets the mode of the regulator. In the mode of operation of the regulator, in the function of compensation of reactive power, a logical signal of the 1st signal is generated at the output of the SPR 8, and in the mode of operation of the voltage regulation function, a signal of the logical 0.

This signal controls the mode of operation of analog switches 3 and 4. When a logic switch 0 appears at the switch off output, this signal goes to the second control inputs of the analog switches 3-4, and the NOT 17 logic element goes to the first control inputs of analog switches 3 -four. In this mode, analog switch 3 permits the passage of a signal proportional to the deviation

5 voltage from the output of ION 1 to the input of the precision rectifier 5, while the analog switch 4 permits the passage of Uoni to the second input of the analog circuit 6 summation.

0 When a PRR 8 output appears, logical 1 is sent to the second control inputs of the analog switches 3-4 through the logical element NOT 17 a logical O and to the first control inputs of the analog switches

5 switches 3-4 - logical 1. In this case, analog switch 3 permits the passage of a signal proportional to the value of the reactive power from the output of the HLR 2 to the input of a precision rectifier

0 5, while the analog switch 4 permits the passage of U0n2 to the second input of the analog summing circuit 6.

The reference voltage U0nt determines the dead zone of the regulator in the voltage control mode on the tires of the unloading unit, corresponding to the change in voltage when connecting one section of the compensator capacitors.

The reference voltage U0n2 determines

0 the dead zone of the controller in the reactive power compensation mode, corresponding to the change in the value of reactive power when one section of the compensator capacitors is connected.

5 The signal from the output of the analog switch 3 is fed to the input of the comparator 7 determining the sign of the signals. A positive signal from the output of the analog switch 3 corresponds or decreases

0 the voltage on the tires of the load node is lower than the allowable value, or the value of the reactive power of the inductive load consumed by the node. In this case, at the direct output of the comparator 7,

The 5th sign of the signals appears logical I, which is fed to the second input of the second logical element ZI-NE 15, thereby allowing the passage of pulses from the generator 11 pulses to the input of the addition +1 of the reversing counter 20. On the inverse

the output of the comparator 7 appears logical O, which is fed to the second input of the third logical element ZI-NOT 16, thereby prohibiting the passage of a pulse from the generator 11 to the input of the subtraction bus -1 of the reversing counter 20.

The negative signal from the output of the analog switch 3 corresponds to an increase in the voltage on the tires of the load node above the permissible value. At the same time, the output signals of the character definition comparator 7 change their value and thus enable the operation of the reversible counter 20 in the subtraction mode and prohibit its operation in the addition mode.

The passage of pulses from the generator 11 is also determined by the state of the logical elements 4IL21 and 4I-NOT 22. The logical element 4 OR 21 performs the functions of restricting the counting down. When occurring at the outputs of the reversible counter 20 logical zeros, logic element 4 OR 21 prohibits the passage of pulses from generator 11 through logical element 3 AND-NOT 16 to the subtraction bus -1 of the reversible counter 20. Logical element 4 AND-NOT 22 performs the function of limiting the my account. When the logical counter 1 AND 4 AND 22 does not appear at the outputs of the reversible counter 20, the passage of pulses from the generator 11 through the logical element 3 AND-NOT 15 to the addition bus +1 of the reversible counter 20 is prohibited.

The controller operates in voltage maintenance mode on the load node tires. A signal proportional to the voltage deviation is fed from the output of the analog switch 3 to the input of a precision rectifier 5, at the output of which a rectified voltage is formed. This voltage is applied to the first input of the comparator 9, the reset of the summing counter, and to the first input of the comparator 10, the start of the pulse generator.

If the voltage at the output of the precision rectifier 5 corresponding to the voltage deviation on the load node tires is less than the voltage from the output of the analog summing circuit 611out5 and outb, then logical output O appears at the output of the pulse generator comparator 10, which prohibits the operation of the generator 11 In this case, the summing counter 13 is in the zeroed state, the signal at the output of the DAC 18 is zero, and at the output of the analogue summation circuit 6, the signal is equal to UonL

In this case, the voltage from the output of the precision rectifier 5, corresponding to the deviation of the voltage on the tires, is less than the dead zone of the Uoni and the regulator is in a retarded state.

Suppose that in the time interval

 (Fig. 2, Output 5) the signal proportional to the voltage deviation increases to a certain steady-state value (time, ti), while at

0 time to it will be above the dead zone Uoni, then the comparator 10 starts the pulse generator and a high potential at its output (FIG. 2, Out.10) enables the generator 11 and 5 pulses, the output pulses of which go through the logical element 3 AND-NOT 15 to the input of the addition bus + G of the reversible counter 20 (FIG. 2, Vyh.11) and to the summing input of the counter 13. Reversible

0, the counter 20 starts counting pulses from the generator 11 in the addition mode, and at its outputs high potentials appear corresponding to the binary code 1: 2: 4: 8 received at the input of the register 23 of the memory.

5 A change in the logic code combination at the inputs of the summing counter 13 leads to a stepwise increase in the output voltage of the DAC 18 (FIG. 2, B, S 18), which is fed to the second input of the comparator 9 resetting the summing counter and to the first input of the analog summing circuit 6. In the latter, the voltage is summed up from the output of the DAC 18 and U0ni (FIG. 2, V.6), after which the resulting

5, the signal from its output enters the second input of the comparator 10 run.

At time t2, when the potential from the output of circuit 6 becomes greater than the potential from the output of precision rectifier0 5 (fig. 2, output 5, output 6), the start comparator 10 is triggered and the low potential at its output prohibits the operation of the pulse generator 11 that leads to stopping of the summing counter 13 and reversing

5 counter 20. The triggering of the comparator 10 also leads to launching through the element 3 AND-HE 14 the one-shot 19 and forming a pulse at its output (FIG. 2, Out 19), which enters the readout bus of the register of the memory 23, leads to transmission a digital code signal from a register to an input of a block for switching on sections of capacitors, the connection of which leads to a decrease in the voltage deviation to an acceptable value, which is determined by U0ni. Then, at the instant of time, the signal, proportional to the voltage deviation from the output of ION 1, changes its magnitude smaller than Uoni. In this case, the voltage from the output of rectifier 5 becomes less

the output signal of the DAC 18, which triggers the reset comparator 9 and the signal at its output (FIG. 2, Vyh.9) causes the counter 13 to be reset and the DAC 18 to return to the initial zero state. The circuit goes into inhibited mode of operation.

With a further decrease in the voltage at the load node buses, the equilibrium state of the regulator changes, the previous operation cycle repeats, and the digital code at the input of the register 23, which defines a new combination of switching on capacitor sections, changes.

When the load decreases and, consequently, the voltage increases on the tires, the sign of the signal from the output of ION 1 and the signals from the outputs of the comparator 7 (figure 2, time point and) change. Comparator 7 prohibits the passage of signals from the generator 11 pulses through the logic element ZI-NOT 15 to the input of the addition + T of the reversible counter 20 and allows them to pass through the logic element 3 AND-NOT 16 to the input of the subtract -1 of the reversing grid 20, at the time ts, this triggers the comparator 10, starts the generator 11 and changes the code combination from the output of the counter 20 leads to the disconnection of the necessary sections of the capacitors (time moment te). At time t, the DAC 18 is reset, while the voltage value from the output of ION 1 is within the permissible limits determined by Worri. As a result, the circuit is in a retarded state.

In reactive power compensation mode. The logical 1 signal from the output of the switch 8 switches the analog switch 4 and analog switch 3, while the output of analog switch 3 contains a signal proportional to the reactive power of the load, and the output signal of analog switch 4 determines the dead zone of the reactive power controller Uon2 (FIG. H). In the case when the signal proportional to the reactive power of the load does not exceed the dead band of the regulator, the summing counter 13 is in the zeroed state, the voltage at the output of the DAC 18 is zero. In this case, at the output of circuit 6, the voltage is equal to Uon2. In this case, the voltage from the output of the precision rectifier 5 is less than the voltage from the output of circuit 6, i.e. Uon2 and the start comparator 10 prohibits the operation of the generator 11 pulses.

At time point to, when exceeded by a signal proportional to the reactive

the load power from the output of the rectifier 5, the voltage Oop2, triggers the comparator 10, which initiates the generator 11, and the pulses from the generator output go to the input of the counter 13 and the input of the reversible counter 20. Since the signal proportional to the reactive power of the load inductive character, does not change its sign, the comparator 7 is in an altered state with any change in the magnitude of the reactive power of the load. Therefore, the comparator 7 prohibits the operation of the reversible counter 20 in the subtracted mode. When the generator 11 is operating, the output voltage of the DAC 18 increases, while the output voltage of the analog circuit 6 of summing is equal to UBbix6 U4an18 + Uon2 (FIG. 3, Output 18, Output 6).

At the time ti, when the voltage from the output of the rectifier 5 is less than the voltage from the output of circuit 6, the comparator 10 is turned off and the generator 11 is stopped, while the code combination is transmitted from the outputs of the register 23 using the AND-3 logic element 14 and one-shot 19. This digital code defines the necessary combination of disconnecting capacitor sections.

With a further increase in the signal from the output of the rectifier 5 (Fig. 3, the time instant ta), the operation of the regulator is completely repeated, and at the time instant tc the capacitor sections switch.

Suppose, at time t.4, there is a decrease in the signal proportional to the reactive power of the load. Then at time ts, the voltage from the output of the DAC 18 becomes greater than the voltage from the output of rectifier 5, the reset comparator 9 is triggered and the logical 1 from its output is turned by the summing counter 13 and through the logic element 2 and 12 the input of which contains a logical unit from the output of the SPR 8, zeroed the reversible counter 20. Thus, the counters 13 and 20 operate in the same mode, i.e. in the summation mode. In this case, the regulator again goes into the mode of changing the code combination, and at the time moment te when the condition for transmitting the digital code to the input of the switch-on unit 24 is met, the capacitor sections are switched. With a further change in the reactive power of the load, the operation of the regulator is completely repeated.

Using the controller allows you to automatically change its mode of operation or programmatically, or on commands

dispatch control systems. In this case, reactive power compensators of the power supply system can meet the requirements of the power supplying organization for reactive power compensation, as well as stabilize the voltage at the load nodes.

Claims (1)

An Adaptive Reactive Power Compensator Controller containing a reactive power sensor connected to the current and voltage transformer outputs, a precision rectifier connected by an output to the first inputs of a reset counter of the summing counter and a comparator of the pulse generator start, the output switch connected to the first the input of the logic element 2 And, the second input of which is connected to the output of the comparator reset the summing counter and to the first input of the summing account The output, to the first input of the reversible counter, is an analog summation circuit connected by the first input to the output of the digital-to-analog converter and the second input of the comparator resetting the summing counter, and the output to the second input of the pulse generator comparator, the output of which is connected to the first input of the first logic element 3 AND-NOT and the input of the pulse generator connected by its output to the first inputs of the second and third logic elements 3 AND-NOT and to the second input of the summing counter, while the outputs of the sum the world counter is connected to the inputs of a digital-analog converter, and the outputs of the second and third elements 3 NAND are NOT connected to the second and third inputs of a reversible counter connected by their outputs to the inputs of the memory register and the inputs of the forward and reverse counters; They are connected to the capacitor switching unit, and the outputs of the forward and reverse counter stops are connected to the third inputs of the first and second elements 3 AND-NOT and to the second and third inputs of the second and third elements 3 AND-NOT responsibly, a comparator for determining the sign of the signal coupled by direct and inverted outputs, respectively, to second inputs of the second and third elements 3 AND-NO, and a one-shot connected to the output of the first element 3 by NAND, and the output to the first memory register input, characterized in that, in order to expand its functionality, a voltage deviation meter, two analog switches and a logical element NOT are added to it the input of the voltage deviation meter connected to the output of the transformer voltage, and the output to the first input of the first analog switch, the second input of which is connected to the output of the reactive power sensor, the output of the program mode switch is connected to the second the control inputs of the first and second analog switches and through the logical element NOT to the first control inputs of these switches, the first and second inputs of the second analog switch connected respectively to the reference voltage, and its output to the second input of the analog summation circuit, the output of the first analog switch is connected to the input of the precision rectifier and to the comparator to determine the sign of the signal. a "xt to t, ti ti b, tr ts b 9o2. 2 tz fig.Z tt ts