SU1644232A1 - Memory with error detection and correction - Google Patents

Description

The invention relates to automation and computer engineering and can be used in memory devices made on multi-bit integrated circuits.

The purpose of the invention is to increase reliability. 5 of the device due to the detection and correction of modular errors by converting them into one-time accurate signs characterizing the presence of an error and the quality of its correction. 10

The drawing shows a block diagram of a device.

The device contains blocks 1.1,1.2,1. g encoding, a group of r-bit memory modules 2, blocks 3.1, 3.2 ..... Z. g decoding, block 4 adders, a group of 5 elements 5.1,5.2 5. Ethyl OR, a group of 6 two-input elements of type I, a group of 7 triggers 7.1,7.2 ..... 7.S, block 8 of indicators 8.1,

8.2, .... 8. (Sg), decoder 9, switch 20. The diagram shows the input 11 of the device installation, the group 12 of the information inputs of the device, the group 13 of the information outputs of the device, the first group of 14 address inputs of the device, the second 25 paradise group of 15 address inputs of the device, a group of 16 control inputs of the device, including the signal inputs Access and signal Read-write.

Pre-30 coding blocks 1.1, 1,2, ..., 1.g are assigned for converting k-bit words of input information into n-bit trees containing information redundancy necessary for detecting and correcting errors. Each of r coding blocks processes p bits of input information, where p =! </ R, and r is the number of information inputs (bits) of memory modules. Coding blocks are functional converters corresponding to a certain truth table, and can be performed using a combinational logic circuit or read-only semiconductor memory 45 (EPROM). Coding may be performed, for example, based on a Hamming code.

The first input of the first memory module is connected to the first output of the first coding unit, etc. The first input of input 50 of the memory module is connected to the second output of the first coding block, the second input is connected to the second output of the second coding block, etc. , Blocks 3.1, 3.2, .... Z.g decoding 55 are designed to detect and correct errors. Each of the decoding units processes S bits of the output information of the memory unit. Block 3.1 processes the output information corresponding to that recorded in memory from block 1.1, similarly the remaining blocks of encoding and decoding are connected. The coding and decoding units have mutually agreed truth tables that allow the detection and correction of errors of a certain multiplicity, for example, single errors or single and double errors. Decoding blocks, like coding blocks, are functional converters defined by the truth table, and can be implemented using a combinational logic circuit or an EPROM.

The adder block, consisting of η two-input logic addition elements, modulo 2, is designed to detect errors in η-bits of corrected information. The group of elements 5.1,5.2, .... 5. S is used to group error signals according to their belonging to the memory modules. Item group

6.1.1 ..... 6.S is used to generate an error signal.

The decoder 9 is designed to select a specific column of microchips of the memory block, switch 10 - for the initial installation of triggers 7 groups.

The device operates as follows.

In the Recording mode, the information words arriving at a group of 12 inputs of the device containing binary digits are converted in blocks 1.1, 1.2, .... 1.g 35 to g words of S digits, which are written to the cell of memory unit 2 addressed to .v according to the code on inputs 14 and 15 of the device. The high-order bits of the address code (inputs 15) through the decoder 9 select the column of the matrix of memory chips, and the low-order bits of the address code (inputs 14) select the memory cell of the selected microcircuits. Redundancy information in step We write B ⁰ and storing the words in the memory unit 2 formed by coding blocks 1 used in the future for detecting, diagnosing and correcting errors in the read information.

In the Read mode, a word is sampled from memory block 2 in accordance with the address code at inputs 14 and 15 of the device. The read η-bit word (n = r »S) goes to blocks 3.1, 3.2, .... З.г decoding, each of which performs an error detection operation for

S-bit part of the word. Blocks 3.1, 3.2 .....

Zg decoding corrects each of all S bits of the data arriving at them, and, in the aggregate, an η-bit redundant word, which includes both bits of the main information and η-bits of additional bits. In this case, the corrected discharges arrive at the outputs of the device 13, and all η discharges taken from the inputs and outputs of the decoding units are compared in adder block 4 using η two-input adder elements modulo 2, which detect discharges containing errors. In the r-input elements 5.1, 5.2, .... 5.S of the OR type, the error signals identified in block 4 are grouped, relating to each row of memory chips. Through a matrix of two-input elements

6.1.1 ..... 6.Sg, to the first group of inputs which receive error signals from elements 5, and to the second group of inputs, sample signals from the decoder 9 according to the signal. The error signals are recorded in triggers 7.1.1,7 .Sg, each of which displays the presence of an error in the corresponding memory chip using the indicators 8.1.1, ..., 8.Sg

Before starting the operation of the device using switch 10, the triggers are set to zero.

With the complete failure of any multi-bit 2.I.J memory chip, an r-fold error occurs (g is the number of bits of one memory chip). At the same time, only one error arrives at the input of each of the blocks of 3.1 З.г decoding, where it is detected and corrected. In the event of correlation failures in several memory microcircuits, for example, failures of a certain category, a multiple error is also generated, it is also converted into a series of single errors at the inputs of blocks 3.1 ..... Z. g. In the same way, the device responds to the complete failures of a number of memory chips if these chips are in different columns of the memory matrix. In case of complete failure of two microcircuits in one column, a 2-fold error will be presented as r double errors, i.e. the transformation of multiple errors into small errors is implemented.

Claims (1)

Claim A memory device with error detection and correction, comprising a coding unit, a decoding unit, a group of r-bit memory modules, a decoder, the output of which is connected to the inputs of a sample of memory modules of the group whose address inputs are combined and are the address inputs of the first group of the device, the addresses of the second group the devices are connected to the inputs of the decoder, the access and replacement inputs of the group memory modules are combined and are the corresponding inputs of the device, which is different. that, in order to increase the reliability of the device, a group of (g-1) encoding blocks, a group of (g-1) decoding blocks, an adder block, a group of OR elements, a group of AND elements, a group of triggers, the inputs of the encoding blocks of a group are combined and are the information inputs of the device, the outputs of the group coding units are connected to the information inputs of the group memory modules, the outputs of which are connected to the corresponding inputs of the group decoding units and to the inputs of the first group of the adder block, the outputs of the blocks are decoded I groups are connected to the inputs of the second group of the adder block and are information inputs of the device, the outputs of the adder block are connected to the inputs of r-bit elements OR groups, the output of each element! and OR groups connected to the first input of the corresponding element AND group, the second input 'of each element AND group is connected to the decoder and to the inputs of the sample memory modules of the group, the outputs of the elements and groups are connected to the inputs of the corresponding triggers of the group, the outputs of which are the control outputs of the device, the outputs group trigger synchronization are combined and are the device synchronization input, group trigger installation inputs are combined and are the device installation input.