SU1626257A1 - Analog signal multiplier - Google Patents

Abstract

The invention relates to devices intended to multiply electrical signals, and can be used in anagolic computing machines. The aim of the invention is to increase accuracy. The analog signal multiplier contains the first through sixth amplifying transistors 1-6, the first through fourth operational amplifiers 7-10, the first to the fifth scaling resistors 11-15, the first 16 and second 17 current sources, the first 18 and second 19 input buses the first signal-multiplier, the first 20 and second 21 input buses of the second signal-multiplier, the first 22 and second 23 output buses of the low potential bus 24. The operation of the analog signal multiplier is based on the implementation of the variable slope method, with an increase in the accuracy of multiplication achieved by estimating the nonlinearity of the base-to-emitter junction characteristics of the amplifying transistors. 1 il. 22 Ј 14. Oy oh by x | s gh

Description

The invention relates to devices designed to multiply electrical signals, and can be used in analog computers.

The aim of the invention is to improve the accuracy.

The drawing shows a functional diagram of an analog signal multiplier.

The signal multiplier contains the first to the sixth amplifying transistors 1-6, the first to the fourth operational amplifiers 7-10, the first to the fifth scaling resistors 11-15, the first 16 and second 17 current sources, the first 18 and second 19 input buses of the first the multiplier signal, the first 20 and second 21 input buses of the second signal multiplier, the first 22 and second 23 output buses, the low potential bus 24;

Analog signal multiplier works as follows.

When connecting load resistors to the first 22 and second 23 output buses and the initial bias voltage to the input buses 18-21, the signals are transmitted by the first 7 and second 8 operational amplifiers to the emitters of the first 1 and second 2 amplifying transistors, causing a change in current distribution through the first 11 and second 12 scale resistors, as well as emitters of the third 3 and fourth 4 amplifying transistors, causing a change in the current distribution through the fourth 14 and fifth 15 scale resistors. In this case, with the potential at the input bus

18, greater potential at the input bus

19, more current flows through the first 1

and. the fourth 4 amplifying transistors, and the smaller one through the second 2 and third 3 amplifying transistors. Cross-switching of the collectors of the amplifying transistors in the ideal case leads to unchanged potentials at the output buses 22 and 23 at a constant current.

The stable collector currents of the fifth and sixth 6 amplifying transistors are provided by connecting these transistors to the negative feedback circuit of the third 9 and fourth 10 operational amplifiers. If the potentials on the input buses 10 and 21 are equal, the potentials of the emitters of the fifth 5 and sixth 6 amplifying transistors are equal, which ensures the absence of current through the third large-scale resistor 13, When the voltages are unbalanced on the input buses 20 and 21, the current through the third large-scale resistor 13 changes It is directly proportional to the amplitude of the voltage between the non-inverting inputs of the third 9 and fourth 10 operational amplifiers.

If a differential voltage is applied to the input buses 20 and 21, then the increments of the collector currents of the fifth 5 and sixth 6 amplifying transistors are the same in magnitude, but different in sign.

When a signal is applied to the input buses 18 and 19, the emitter currents of the first 1 and second 2 amplifying transistors are redistributed, as well as the third 3 and fourth 4 amplifying transistors, If we choose equal to the resistance values of the first 11, second 12, fourth 14 and fifth large-scale resistors, when the first signal of the multiplier on the input buses 18 and 19 is zero, the second signal of the multiplier is suppressed by redistributing the currents of the first 1, second 2, third 3 and fourth 4 amplifying transistors Acting on the input bus bars 20 and 21.

When the magnitude of the first and second signal multipliers is changed, multiplication of these signals is achieved, the nonlinearity of the base-emitter characteristic of the amplifying transistors is compensated by the operational amplifiers and the steepness of the control is determined only by the resistance value of the scale resistors 11-15.

The difference in the output currents of the output busbars 22 and 23 is determined by the expression

122-123 - Vx

Ri3

where Vx, Vy - the first and second signal factors;

IQ is the current through the first (second) output bus 22 (23);

Rn, Ri3 are the resistance values of the first 11 and third 13 scale resistors.

Thus, the analog signal multiplier is characterized by a higher accuracy of operation, provided by compensating for the smallest non-linear components of the product signal.

Claims (1)

Invention Formula An analog signal multiplier containing the first to sixth amplifying transistors, first to fifth scale resistors, first and second current sources, the base of the first amplifying transistor is connected to the base of the fourth amplifying transistor, the collector of which is connected to the collector of the second amplifying transistor, the base of which connected to the base of the third amplifying the transistor whose collector is connected to the collector of the first amplifying transistor, the collectors of the first and fourth amplifying transistors are respectively the first and second output buses of the analog multiplier, the first terminals of the first and second large-scale resistors are interconnected, the emitter of the fifth amplifying transistor through the third a large-scale resistor connected to the emitter of the sixth amplifying transistor, the emitter of the fifth amplifying transistor is connected to the first terminal of the first source As the emitter of the sixth amplifying transistor is connected to the first output of the second current source, the second outputs of the first and second current sources are connected to a low potential bus, characterized in that, in order to improve accuracy, first to fourth operational amplifiers are introduced into it. , the output of the first operational amplifier is connected to the base of the first amplifying transistor, the emitter of which is connected to the second output of the first large-scale resistor and to the inverting input of the first operational amplifier, non-inverter yuschy whose input is the first input bus of the analog multiplier signal, the output of the second operational amplifier is connected to the base of the second amplifying transistor, the emitter of which is connected to the second output of the second large-scale resistor and the inverting input of the second operational amplifier, the non-inverting input of which is the second input bus of the first signal multiplier , the output of the third operational amplifier is connected to the base of the fifth amplifying transistor, the collector of which is connected to the first terminal of the first m the scaling resistor, the emitter of the fifth amplifying transistor is connected to the inverting input of the third operational amplifier, the non-inverting input of which is the first input bus of the second multiplier signal of the analog multiplier, the output of the fourth operational amplifier is connected to the base of the sixth amplifying transistor whose emitter is connected to the inverting input- a fourth op-amp, the non-inverting input of which is the second input bus of the second analog multiplier signal comer