SU1626176A1 - Digital frequency and phase meter for harmonic signals - Google Patents

Abstract

Recycling refers to the radio ™ technique of 1 spruce technique and to be used to estimate the frequency and veil frequency of about 1 nl. The purpose of the isobrengig is to increase the accuracy of measuring the phase of the signal and expanding the range of operating frequencies. In the proposed meter, a U-trigger T, registers 8, 20, 21 and 22, a phase estimation forming unit 16, an adder 18 are entered, which allows a change in the code at input 19 promptly rearrange the meter by the frequency range The meter also contains a comparator 1, a counter divider 4, a snifter 5, a counter 6, a generator 9 of trigonometric functions, the sum is a torus 10, a random access memory (RAM) 11, a quadrant 13 and block 14 search maximum. 9 silt

Description

The invention relates to radio measurement technology and can be used to estimate the parameters of a harmonic signal — phase and frequency and noise.

The purpose of the invention is to improve the accuracy of measuring the signal phase and expanding the range of operating frequencies.

1 and Fig. 1 shows a block diagram of a digital meter for the frequency and phase of a signal; Figures 2 and 6 illustrate examples of the railizacin trigonometric function generator, quad, maximum search unit, phase evaluation generation unit and synchronizer, respectively; 7-9 are signal plots explaining the operation of the meter and the synchronizer

The digital frequency and phase meter of the signal contains () a comparator 1, the input of which is the first input 2 of the meter, the D-flip-flop 3, the D-input of which is supplied with the level of a logical unit, the counter-divider 4, the synchronizer 5, serially connected counter 6, information the input of which is the device’s fifth input 7, register 8, generator of trigonometric functions 9, adder 10, random access memory 11, register 12, quadrant 13, maximum search unit 14, the second input of which is the third meter input 15 and unit 16 phase evaluation, the output of which is the first output 17 of the meter, serially connected adder 18, the first input of which is the fourth input 19 of the meter, registers 20 and 21, and also the register 22, the second input 23 of the meter, the second output 24, moreover, the combined counting inputs of the counter-divider 4, counter 6 and the clock input of the register 20 are connected to the input 23 of the meter, the first output of the counter-divider 4, the second input 23 of the meter, the output of the D-trigger 3 and the second output of the counter-divider 4 are connected respectively to the inputs 25.1-25.4 syn 5, and the synchronization input of the generator 9 trigonometric functions, the combined synchronization inputs of the registers 12 and 22, the phase estimation forming unit 16, the first 26.1 synchronization inputs of the maximum search unit 14 and the control input of the random access memory 11, the combined synchronization input the quadrant 13 and the second 26.2 synchronizing input of the maximum search unit 14, the combined control inputs of the adder 10 and the maximum search block 14, the combined inputs of the initial installation of the counter 6, the register 20 and the third 26. 3 synchronization input of the maximum search unit 14, the address inputs of the random access memory 11, the control input of the generator 9 of the trigonometric functions and the combined synchronization inputs of the registers 8 and 21 are connected respectively to the first 27.1 - eighth 27.8 outputs of the synchronizer 5

The trigonometric functions generator 9 (FIG. 2) contains a serially connected register 28 between the input and output, an adder 29, a switch 30, the second input of which is the second input of the generator of trigonometric functions, the output 31 of which is additionally connected to the second input of the adder 29 , the persistent storage device 32, the register 33, the combined synchronizing inputs of the registers 31 and 33 are synchronizing, and the combined synchronizing input of the register 28 and the control input of the switch 30 are controlling by moves of the generator of trigonometric functions.

one

Quad 13 (fig.Z) contains between the input and output sequentially

connected permanent memory 34, a register 35, the synchronization input of which is a quadra synchronization input, and an adder 36, the second input of which is connected to the output of the permanent memory 34.

Maximum search unit 14 (Fig. 4) contains a register 37 connected in series, switch 38, the second input of which is the second input of the maximum block, register 39, comparison unit 40, the second input of which is connected to the output of register 37, OR 41, whose output connected to the synchronization input of the register 39, as well as serially connected counter 42 and the register 43, the output of which is the output of the maximum search block, and the clock input of the register 37 is connected to the first gate input of the comparison block 40 and the first sync input 26.1 for maximum search, the count input for counter 42 is the second sync input 26.2 for maximum search, the inputs to zero for counter 42 and register 43 are connected to the second input of the OR element 41 and the third sync input 26.3, and the control input for the switch 38, connected to the second gate input of the comparison unit 40, is the control input of the maximum search unit.

The phase evaluation generating unit 16 comprises serially connected registers 44 and 45 between the input and output, a persistent storage 46, an inverter 47, an adder 48, a persistent storage 49, a register 50, and also a permanent storage 51 whose input is connected to register 44, and the output - with the second input of the adder 48, the element EXCLUSIVE OR 52, the inputs of which are connected to the input and output of the high bit register 44, and the output - with the input of the high bit yes register 45, and the output of the high bit register 45 connect to the input of MSB PROM device 49, the output MSB of register 44 - to the input of MSB register 50, registers siyhroniziruyuschie inputs 44 and 45 and combined in-

The synchronization input of the block and the synchronization input of the register 50 are the second input of the block.

The synchronizer 5 (FIG. 6) contains a D-flip-flop 53, the D-input of which is the input 25.J of the synchronizer, D-flip-flop 54, the D-input of which is fed to the level of the logical unit, and the output is connected to the 1) input D-trnggera 55, the output of which is connected to the input to the zero setting of 1) -thrngger 54 and the first input of the element Ш1И 56, the counter 57, the output of the high-rcdr of which is connected to the synchronizing input of the D-trehger 58 and the second the input of the element Ш1И 56, D-trmgger 59, the output of which is connected to the D-input of the D-flip-flop 60, the synchronous wiring of the input of which is connected to the synchronizing inputs D-flip-flops are 53 hours 55, counter 57 and is a synchronizer input 25.2, and the output is connected to the input to the zero setting of the D-flip-flop 59 and the counter 57, D-flip-flop 61, the synchronizing input of which is connected to the synchronizing input of the D-flip-flop 59 is the synchronization input 25.4 of the ator, and the output is connected to the D-input of the D-flip-flop 62, the output of which is connected to the D-input of the D-flip-flop 63, the sync input of which is combined with the sync inputs of the U-flip-flop 54 and 62, the input 25.1 of the synchronizer, and the output is connected to the inputs to the zero setting of the D-flip-flops 58, 61, 62, with the level of the logical unit is supplied to the D-triggers of the D-flip-flops 59 and 61.

Digital meter frequency and phase of the signal works as follows.

At the input 2 of the meter enters a narrow band signal with noise ()

U (t) V cos (2iTfct + FS) + v (t),

where V is the amplitude of the signal;

fc is the unknown frequency of the signal constant over the measurement interval, duration T, fc e (Ј „, ,n + 2Р), where Ј„ is the lowest possible value of the frequency of the signal; f f + G-center frequency

signal; 2F "ffl - range of possible values

signal frequency;

PC is the initial phase of the signal to be estimated, i.e. sig phase

cash; 1 at the time, RS 6 (0.2 G);

v (t) - uchband noise. Such a signal is generated using a band-pass filter, the bandwidth of which is equal to the range 2F of the signal frequency uncertainty.

A signal with a follow-up period T, defining the measurement interval, is formed at the output of the higher bit of the R-partial (R log, frT) counter-divider 4 (Fig. 86) from the clock signal

Frequency frequency и t and is applied to c: :: 25.4 synchronization of the actor 5. The front of this signal is the beginning of the next measurement interval.

Comparator 1 generates pulses

null intersections with a frequency equal to the frequency of the input signal. The fronts of the pulses coincide with the moments of crossing the input signal of the zero level with a positive signal.

izvodnoy (Fig.76). Zero-crossing pulses arrive at the D-flip-flop clock input Z. A signal from the AND-th digit of the counting is given to the input of the Z-D flip-flop setting Z.

chica delhi gel 4 (). This signal has the form of a meander and the period of the following T, and

H int L0; nr / 2f) f

where is not 1a part of number-X.

Thus, the D-flip-flop 3 is set to the state of the logical unit by the first impulse of the null-intersection received on the snc

D-flip-flop input 3 during each n-th (n 1, 2N) positive half-period of the meander - the so-called window. The time period for the windows is related to the range.

2F frequency uncertainty of the input signal: 1 p. 1 / 2F.

The duration of the Јfl window must exceed the period of 1 / fc of the input signal, so that the window is guaranteed

hit at least one zero-crossing pulse. It is convenient to form C0 1 / 2To, which is certainly more than the period of the input signal. The number of windows at each interval is

neither the duration of T is constant and equal

but n.

Thus, for the period of following the Tp windows, at the output of the D-flip-flop 3 a single

71

zhtelny front, which corresponds in time to a decimated approximately fft / 2F times zero-intersection pulses (),

The thinned zero-crossing pulses are fed to the synchronizer 5, to the D-input of the D-trchgera 53, the clock input of which receives the clock frequency fT (fig.7d). Thus, at the output of D-flip-flop 53, thinned and synchronized zero-intersection pulses () are generated and synchronized along the clock signal fronts.

The algorithm for processing a sequence of zero-crossing synchronized pulses in order to measure the frequency and phase of a signal includes the following steps 4 In the measurement interval (T / 2, T / 2), a discrete analog of the square module Z (f) of the complex correlation integral (spectrum) Y (fg ) on a discrete set of reference frequencies fj6 (fM, f H -t- 2F)

Z (f.HY (fe) | () |,

v n,

where f c + (f, 2, .. „,, L -

H 1 / 2T - (gn fi / 2F) -

0

6176

five

0

five

AT

L (2F / uf) + l is the number of reference

frequencies;

N is the number of thinned zero-intersection pulses received during the measurement interval (-T / 2, T / 2), i.e. quantification

tn € (-T / 2, T / 2) is the arrival time of the edges of synchronized zero-cross-section pulses, measured from the center of the interval (-T / 2, T / 2) (hereafter, also the designation t is used)

The frequency c is determined at which Z (fn) takes the largest value out of those that exceed a certain threshold — the detection threshold. The frequency f is is0

five

with a signal frequency estimate.

Is found in terms of valid

Noah Yc (f.) sinZ7fet and imaginary and

AN..A

Vf 5 osZ7t

 - d

correlation integral Y (fp) for the frequency fe, the phase estimate ™ of the signal, referred to the mid-interval

eLn

gt parts of complex measurement, i.e. signal phase I

initial grade

r id -. 0, with Yc (fg) 0, Y, (f.) O,

arctg Yc (fg) / Yg (fЈ) J + gtt, g 1 1, with Yg (fj) 0.

2, with Yc (fg) c-0, Ys (fe) 0.

The above algorithm is implemented in the device as follows.

At the beginning of the measurement interval, the inputs of the initial installation (R + 1) -pa- aral of the counter 6 and register 20 are given a pulse of the initial installation from the synchronizer output. In this case, counter 6 is set to -3/4, and register 20 is set to

standing

state 2

R +

 9

n

fd-fr-

Where

 - the fractional part of the number X; 0 (,

, R +

2 code lower frequency fH. Pulses of clock frequency fT, arriving at the input of counter 6 and sync

45

50

55

The lowering input of register 20 changes their state, and the state of counter 6 with each clock pulse increases by one, reaches a value (2Rtl - 1), after which the counter overflows (switches to state O) by the next clock pulse in the middle measurement interval In the second half of the measurement interval, the state of counter-a 6 increases from 0 to State m of counter 6 at an arbitrary time t, measured from the middle of the measurement interval, represents the 2nuft code of the reference signal sin 2f & ft frequency b. f - “1/2T.

In this case, the change in the state of counter 6 (phase code) from (-3/4 to

2 k / / / h through zero corresponds to a change in the phase of the reference signal sin from a value of -7 / 2 to n / 2 through zero, and an arbitrary state m of the counter 6 is associated with a phase of 27uft by

2faf t 2T -2 + 27i.

where h 0 at 0 Ј t Ј T / 2, h -I at -T / 2 t 6 0.

The state of register 20 increases with each clock pulse by the X value of the low frequency code supplied to the fourth input 19 of the meter and added by the adder 18 to the previous state of the register 20. The (RH) state of the discharge register 20 changes during the measurement interval (- T / 2, T / 2) periodically with a period Tn (2RV (/ tffr) "T and vanishes in the middle of the interval (at time t 0). State M of register 20 at an arbitrary time t is associated with the represented this code phase of the sin 2e fH t reference signal generated in this way with frequency fH (fT / 2R v ratio

R4- (

  2fiM / 2 + 27r,

where r 0, il, Ј2 ,. 4. - integer number of overflows of the adder 18 for the time t (integer number of periods of the reference signal). By changing the code of the lower frequency, it is possible to change the value of the lower reference frequency of the analysis band f and tffT / 2, which expands the operating frequency range of the proposed meter compared to the known, having a fixed setting.

At times tn, a thinned and synchronized zero-crossing pulse records in registers 8 and 21 of the codes m n and Mn, respectively, associated with the phases of the generated reference signals by the relations

2fcftn- + 2fihn,

2fi fHtn - 2Г-Ј +,

0

five

five

0

five

0

five

0

The mn and mp codes are stored in registers 8 and 21 until the next decimated zero-crossing pulse arrives at time tnf,.

At the beginning of each window, the control signal from the output 27.7 of the synchronizer 5 (), the switch 30 of the generator 9 trigonometric functions switches to passing the signal from the register 21. With a cut of this signal, the contents of the register 8 are written to the register 28 of the generator of trigonometric functions. At the same time, the front of the sync pulse from output 27.1 (FIG. 3) of synchronizer 5, the contents of register 21 is written to register 31. The content of the latter, which is the MP code of the phase of the lower reference frequency f., Is fed to the input of the permanent storage device 32 and the second input of the adder 29, where it is summed with the code mn of the phase of the reference frequency D поступ, arriving at the first input of the adder 29 from the output of the register 28

At the end of the control signal from the output of the synchronizer 5, the switch 30 switches to transmitting to the input of the register 31 of the addition results performed by the adder 29. The addition of the results of the addition to the register 31 is carried out every Ј-m (3, ..., L) sync pulse with output 27.1 synchronizer 5. The period of these sync pulses is equal to

Tp / L.

As a result of the (L-1) -fold summation of the contents of registers 28 and 31, in the latter, such numbers A. are sequentially fixed in time.

R + 4

Ae, p mp + - -Јe, p-2,

where fn is the number of overflows of the adder 29 when (t-1) is a multiple of the number of gl to the number of ml.

The numbers Agn are related to the phase 2nfpt of the support signals sin 2 n fjt thus formed, I 1, L by the relation

55

2toetn 2 fM-tn + U-O 27Aftn

 & to C

g „+. (“ -) Ch Gv, p.

A sequence of numbers AP, i

“F

I m 1, L are the addresses at which sequential storage device 32 is alternately retrieved and written to register 33, and then a sequence of alternating real 2 is fed to adder 10 from the alternating real.

+ (t-l) hn 4j sin i |

and imaginary cos 2 iTf j tn cos 2iAЈg, / 2 parts of the function exp (-j2 | Tf «t J / where« - 771..

At the same time, the second input of the adder 10 is readable from the random access memory.

sin

27fe

n

Ycn (fe) 21cos2 fgtp, Mr

ten

8Lp c.

fr I, L are recorded at the corresponding 2L addresses of the random access memory 11 instead of the former amounts (fg) and YenH (fj) stored there, all the L numbers Agn, exp () and all the corresponding 2L sums Y5n (f) and YC (fg) ends before the beginning of the next (n + 2) th window pulse, after which the whole cycle of calculating the numbers Aj) m, exp (-j2irfettH,) and the sums 15 Y5, mi (fe) YC, TH. (f) repeats.

During the first window pulse, the codes m ,, and M, respectively, are written to registers 8 and 21. At the beginning

va 11 to register 12 sequence 20 of the second window codes m and M {re-alternating amounts of real and

4n -, (fe

W

sin

and imaginary

fc.n- | (fe 21 cos 2 / & fetp, rfle, L

rtf

1 Y

s, o

(ff)

component (for n «(fe) 0).

Synchronization of the operation of the generator 9 trigonometric functions and the random access memory 11 provides simultaneous input to the adder 10 pairs of components

And- (sin and sin and slugawch n

rc

myh cos

2frf

h- "

: etp

ech and

cos 2 n f,

e tp

summation results Y (fg)

The registers are 28 and 31 and the formation of the numbers A p and exp (-j2irf g t -) begins. By the beginning of the third on the current window interval, the 2L address of the RAM itself 11 contains the numbers: sin, t, cos), sin 2 / i (f / it (l, cos 2lTf2 t .., sin 2fi fLt ,, cos 2frfLt. By the beginning of the fourth window, the amounts recorded in the operational locking device of 1 for 2L addresses are as follows: sin 2nf, t4 + + sin 27f (t2, cos t, + cos 2lTf4 tan i sin, + sin, cos 21Г +ГЦ + -t- cos 21Tf2. t1, ..., sin, +

35 + sin, cos 2lTf + cos 2nft, tz.

The following accumulation results are recorded in the random access memory (n + 2) window:

eleven

2fif, t, + sin f, tu + ... + sin 2 / iTf, t „lsin cp

2 nЈ, C (+ cos 2 / iTf, t2 + ... + cos Zftf, tn LCOS, tp,

and

2 / ii f / 2t, + sin 2 tif2t2 + ... + sin 2 / iifatn sin 2 "fit,

n Zfaflt, + cos + o .. + cos S.cos.

, . .-- ". -

2 / "flat, + sin + ... + sin 2lTfL | tn 2L.sin,

n1

cos 2 / iffljt1 + cos 2

Uf.tfc

A number of accumulated results can be written shorter

B

(fe) sin 27fetp;

Yc, r (f) Z.cos 2iTfetp, t - T71.

sin

27fe

n

Ycn (fe) 21cos2 fgtp, Mr

8Lp c.

fr I, L are recorded at the corresponding 2L addresses of the random access memory 11 instead of the former amounts (fg) and YenH (fj) stored there, all the L numbers Agn, exp () and all the corresponding 2L sums Y5n (fЈ) and YC (fg) ends before the start of the next (n + 2) th window pulse, after which the whole cycle of computing the numbers Aj) m, exp (-j2irfettH,) and the sums Y5, mi (fe) YC, TH. (f) repeats.

During the first window pulse, the codes m ,, and M, respectively, are written to registers 8 and 21. At the beginning

0 of the second window codes m and M {rewl.

n1

cos

2W. tn Z.CQS 2iifLtp. p "i

Thus, by the beginning of the second window following the considered measurement interval, in the random access memory 11 at the 2L addresses, the corresponding accumulation results for all N processes were recorded.

of the zero-crossing cut pulses of the considered measurement interval — the quadrature components of the complex correlation integrals:

N

Vfe - Wfe, sin eV

VI

Vfe} Yc, vj (fe IEcos, Ј TL.

From the beginning of the second to the beginning of the third window of the next measurement interval, the synchronizer 5 signals the maximum search mode from output 27.4 (Fig. 9e) and puts the digital frequency and phase meter into the search mode for the maximum of the square of the complex correlation module | according to the data accumulated in the random access memory 1 1 H.I previous measurement interval. This signal places adder 10 into the mode of direct data transmission from the first input to the output. The search for the addresses of the random access memory 11, the writing and reading of data in this mode are performed at the same pace and in the same order as in the accumulation. The quadrature components Y5 (f,), Yc contained in random access memory II

 Yc

from from operational storage

the devices and through the register 12 are fed to the address inputs of the permanent storage device 34 of the quadrant 13, as well as to the input of the register 22. At the same time, the data- coming from the generator 9 of the trigonometric functions -sin, cog, sin .to cos C ,,.,. , sin cos 2 n f t and corresponding to the first cut through zero-intersection pulse t. in the new measurement interval, they are recorded at the corresponding 2L addresses of the random access memory I I. At the output of the permanent memory 34, squares of the corresponding and Yc (fg), I l, L are formed, respectively, which are fed to the inputs of the adder 36 directly -Yc (fg) and through the buffer register 35 - Y | (). Each of the value of the square of the correlation integral module formed at the output of the adder 36

rf,), Ys (fa), YC (12), ...,

(fL) alternately read

Z (fg) Y | (fg) + Y (fe), i 1, L

0

five

0

five

0

five

0

five

0

five

The register 37 of the maximum search bit 14 is recorded and compared in the comparison circuit 40 with the threshold code recorded in the register 39. The control signal from the synchronizer output 27.4 for this includes the switch 38 for passing the contents of the register 37 to the input of the register 39 and enabling the comparison circuit 40 to work. If the contents of register 37 exceed the contents of register 39, the synchronization pulse 27.2 (fig. LD) of synchronizer 5 passes through the comparison circuit 40 and carries the contents of the register 37 X (fe) through the switch 38 to the register 39, writes to the register 43 the number t reference frequency fg from counter 42 and fixes in the register 50 of the unit 16 for forming the f.echy estimate the evaluation code of the argument Y (f§), i.e. This component of the spectrum. All subsequent values of the square of the correlation integral Z (fg + (), Z (j p4j.) And so on) formed in the adder 36 are compared to the exceeded threshold and recorded and register 39 b 14 of maximum search as a new threshold of the integral integral Z (fg) until one of them exceeds the contents of register 39 and is written into it as a new threshold. Thus, the search procedure of the maximum continues to Z (f,) inclusive. Counter 42 at each comparison step increases by one, taking the number of I / I, L, coinciding with the reference frequency number t, the square of the complex correlation integral module Z (fj) for which is compared at a given time with the threshold. Resetting the counter 42 and register 43 is performed at the beginning of each measurement interval by a signal from output 27.5 synchronizer 5 (Fig.8g),

The procedure for finding the maximum of the square of the complex correlation integral module 2 (fg) ends after viewing all L values of Z (fp), b - 1, L, and in register 43 it will write the number / reference frequency iЈ for which the value of the complex correlation module integra

l

la Z (fp) is the largest measurement at the given interval. The threshold code is written to the register 39 at the beginning of each measurement interval by the signal from the output 27.5 of the synchronizer 5 (Fig. 1g). Switch 40 switches to pass a threshold code from the third 15 input, measure-

l to the input of the register 39 signal output 27.4 (Fig.9a) synchronizer 5.

Simultaneously with the formation and search for the maximum of the squared modulus of the correlation integral (spectrum modulus), an estimate of its argument (spectrum phase) is formed. In block 16, i phase estimation is formed. Quadrature COCIMHTU p, d,. Yg (fg) and Yc (fe) ko:; pl} - sch. / about the correlation integrator Gg-Otarctg a lYel eJ -eogafY5lfe)

- I

ta- .JO iVu -V, (fg) Yc (fe) 0, 1, -Pb Y5 (fe), Yc (tt,) - 0

with Vc (fp) O

at. L (1 q). 0

At this, slaughter Oe, tg -klyuchennoy in kvl. Chng with r too 1st, Normalized in nocTCHi HOM for: og-.ins ji ieM device i), T-I; IL IIH par d d code fach; (number d) is generated. sign bit cog i ((i P and straightforward, and the number b pi is an element of the NSCNM-M (| SCHEP tiT. 52 in sign bits yd to vc (fg) i- yu; (fg) is given in ci the address of the constant lnn i and "..cc ycTjj-mcTBi h-9 h: rez p: -gi. rp L5

 ikng, and the time of action is the rubber search.i maximum of the search block maxi hma srarnnt vssd L for- mlrch-k.p-l l g; sludge module

i (ffl) KSMP (; KSNOGO CHORRELPHTsOINOGS

int. ran. 1 Y (i) with popog found and between soooo / j determines the maximal one of them Z (fp). Number I, how about p-j j riii if, which correspond

tll

south O JH ch.nosh.- i (fg) and Y (fg) and KOTLJJCIJ: gn-tslt assessment of the hour of hpggy sshnla, hr w. shtg.ets in register 4i b.chookoisk, a) tseng l ar i / mgchpa LMOTO magician of in-tnogo but mod76

sixteen

0

la comes from the output of register 22 through registers 44 and 45 to the address inputs of permanent storage devices 51 and 46, respectively, the outputs of which form the logarithms of the modules of these components (f ") and loga | YC (Јg) | coming to the adder 48 The logarithms of the modules of the actual components logq p) / are pre-inverted by j inverter 47. From the output of the adder 48, the difference code loga / Y c (f.) f - - loga | Y (fg) | . steps into the address input of the permanent storage unit 49, from the output of which the output pulse of the maximum search unit 14 reads into the register 50 the code for estimating the phase of the corresponding component of the spectrum, which is generated by the algorithm

+ b1i + (0,27),

Any value of Y (fg), which is an estimate of the initial phase of the signal, is recorded in the register 50 of the phase evaluation unit 16.

The instrumental error of the signal phase estimate, i.e. the error in the absence of noise v (t) at the input of the meter consists of two main components: the error caused by the quantization effect of the input data and the finite bit size representation of the numbers in the digital frequency meter and signal phase nodes and the error associated with the uncertainty of the position of the thinned zero pulses - intersections with respect to the middle of the measurement interval. The first component is inherent in all digital gauges and is reduced to the required value by an increase in the clock frequency, the presentational depth of the data and the results of the calculations.

The second component is the pr-pna. Signal for phase meters of the signal along its zero-intersections, since in them the measurement of the phase of the signal at known times is measured by measuring the moments of time when the phase of the signal is equal to a known value, for example, (2lfg - ) where

S 0, +, +2, .... Rate:) that error can be calculated by

Df,

where 0 t is the prior uncertainty of the position of the decimated and NT-PULS zero-intersections on the measurement interval, In the known meter, the prior uncertainty of the position of the zero-crossing pulses, punctured by the counter-divider, on the measurement interval is

: fn / 2F - l / 2) fc 1 / 2F.

In this case, the error in the phase measurement in the known meter reaches the value of φ, g (21T / 4FT). For example, at 2F 6 kHz, T 0.025 s, JP, 1.2 °.

In the proposed meter, an increase in the accuracy of the Fachy measurement is achieved by reducing the uncertainty of the position of the punctured zero-crossing pulses. To do this, the thinning of the zero-crossing pulses is performed not with the help of the splitter counter, as in the known meter, but with the help of windows whose temporal position is on measurements are rigidly defined by the meter circuit and the same on all measurement intervals. In this case, the uncertainty of the position of the thinned pulses of zero crossings in the measurement interval does not exceed the signal period l / fc. Consider the component error estimates of the phase in the proposed meter f. 2T / 2TЈs ie approximately E fc / 2F is less than times, than in a well-known meter. For example, at f0 100 kHz and T 0.025 with $ F 0.07 °.

Tests of the proposed meter with the parameters f0 100 kHz, ftf 20 kHz, L 300, T 0.025 s also confirmed its high efficiency.

The meter provides real-time estimates of the frequency and phase of a signal with an a priori uncertainty of its frequency 2F 6 kHz. The accuracy of measuring the phase of the signal is close to the theoretically potential, the losses do not exceed 5 dB over the whole range of signal-to-noise ratios, except for the conditions when an almost pure signal is observed. In this case, the composition

The instrument error of measuring the phase of the hpch.ch.ch.ch account of the uncertainty of the polo / ken of the natural null-peri-hygnus pulsop in the measurement interval does not exceed the calculated value.

Claims (1)

Invention Formula A digital frequency meter and phase of the harmonic signal containing a comparator, the input of which is with the first input of the device, a divider counter, a synchronizer, the first KOTOpoio input is connected to the first output of the counter-divider, a counter whose counter input is connected to the second synchronizer input and is the second the input of the device, the generator of trigonometric functions and the first adder, the first input of which is connected to the output of the generator of trigonometric functions, and sequentially connected random access memory in, the first register, the output of which is additionally connected to the second input of the first adder, a quad and a maximum search block, the second input of which is the third input of the device, the clock input of the generator of trigonometric functions, the combined clock input of the first register, the first clock input of the maximum search block and the control input of the random access memory, the combined clock input of the quad and the second clock input of the maximum search block that controls the input The maximum search unit, the third synchronization input of the maximum search unit, the address inputs of the random access memory and the control input of the generator of trigonometric functions are connected to the first to seventh outputs of the synchronizer, respectively, in order to improve the accuracy of phase measurement and expand the operating frequency range, it contains four registers, an adder, a phase evaluation unit and a D-flip-flop, the D-input of which has the level of a logical unit, the synchronization input of which is connected En with the comparator output, and the output with the third synchronizer input, the second register input is connected to the counter output, and the output is connected to the first input of the trigonometric functions generator, the third register input is connected to the first register output, the output of the phase estimator is the first output of the device and the first and second inputs are connected to the output of the third register and the first output of the maximum search block, respectively, a second adder are connected in series, the first input of which is the fourth input of the devices a, the fourth register, the output of which is additionally connected to the second input of the second adder, and the synchronizing input to the second input of the device, and the fifth register, the output of which is connected to the second input of the general generator ;; trigonometric functions, with the LEAK of the first adder connected to the operational supply input 17 0 five 0 miner device, the counting input of the counter-divider is connected to the second input of the device, the first output of the counter-divider is additionally connected to the installation input of the D-flip-flop, and the second output - to the fourth synchronizer input, the combined synchronous inputs of the third register and the phase estimation generating unit, the first control of the first adder, the combined inputs of the initial installation of the counter and the fourth register, the combined synchronization inputs of the second and fifth registers are connected respectively to the second, fourth, n th and eighth ysodami synchronizer, an information input of the counter is a fifth input device and the second output of the maximum searcher - the second output device. FIG. 2 R Ј Myth one one , 9 ai one e 9 19291 but) J a25.2 B25, V w / sync-tvra g27.5 B27.2 c25.} Well gsinhohoshchbr 27.7 27.1 and -G / 2 25.2PGOSHPLV25 .4 -G 25.7 -L Mr. J synhra - G nizator- | d Chsinho-nizator e 27.4 - F 27.3 - AND 10KNO 1 OKN02 1 QKHQ3 J -G / 2 L all sha 5 Compiled by V.Novoselov Tehred M.Didyk Proofreader M.Demchik Editor and Horn Order 275 Circulation. 176Subscription VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab., A / 5   - - - - - .. Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 FIG. 7 .LII. P P -ITULTT. P | 8 ° JUUITJl J L all sha