SU1624345A1 - Device for frequency difference measurement - Google Patents

Abstract

The invention can be used to quickly measure the frequency difference between 2 highly stable oscillators. The aim of the invention is to increase the speed and pz of a spike in another zone of the measured frequency range. gr ,, for measuring the separation of the frequencies. first and second divide. And 2, 3 often. s, counter 4, shaper of 6 exchange intervals, shaper of 7 short pulses, comparison circuit of the Vydean codes of the delay element 9, integrator 10, anapogs-digital converter 1 of the first to third 5, 12, 13 registers would increase; Strode action and extend the range of the measured frequency difference. 2 Il.

Description

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The invention relates to the field of electrical and radio measurements and can be used to measure the frequency difference required, in particular, when adjusting the reference oscillators of communication equipment according to the source of the reference frequency.

The aim of the invention is to increase the speed and the range of the measured frequency difference.

FIG. 1 shows a functional diagram of the device; in fig. 2 - timing diagrams for the operation of the device.

The device contains a frequency multiplier 1, the first frequency divider 2 (DF), the second DCH 3, counter 4, third register 5, shaper 6 time slots (FVI), shaper 7 short pulses (FKI), block 8 code comparison (BSC), element 9 delay, integrator 10, analog-to-digital converter (ADC) 11, the first 12 and second 13 registers. The second input of the device through serially connected multiplier 1 frequency, FVI b, integrator 10, ADC 11, the first and second registers 12, 13, BSK 8, FCI 7 and the counter 4 is connected to the third register 5. The first input of the device through the first DCh 2 and the second DCH 3 is connected to the second inputs of the counter 4 and the third register 5. The output of the first DCH 2 is connected to the second input of the FVI 6, and the output of the latter through 1 delay element 9 is connected to the second inputs of the integrator 10, the first and second registers 12, 13, FCI 7. Output The first register 12 is connected to the second input of the BSK 8. Its second you od and the output of the third register 5 are information device outputs.

FIG. 2 shows the signals at the outputs of a - multiplier 1 frequency, b - the first DCH 2, c - FVI 6, g - delay element 9, d - integrator 10, codes of numbers, e - in the first register 12, w - in the second register 13, h is the signal at the output of the FKI 7 and u is the state of the counter 4 (2i).

A device for measuring the frequency difference works as follows.

The frequency of the signals received at the second input of the device to frequency multiplier 1 is increased K times (2a), and at the first input of the device decreases by n times in RF 2 (26). FWI 6 generates pulses (2c), starting at the time of the signal front with DCH2 and ending with the arrival of the second (after this) signal front with the multiplier 1 frequency. Their duration t € Ti / K, 2Ti / K, where Ti is the period of the signal at the second input, in the integrator 10 is converted into voltage U (2e), which is converted into a code and pulse front with

delay element 9 is recorded in register 12 (2c), since the pulse duration t characterizes the current phase difference of the compared signals (its change by Ti / K corresponds to the phase difference change by 2 l / K), the code change at the output of the register 12 per unit lower bit corresponds to a change in the phase difference of 2 l / CU, where P is the difference of numbers, respectively, A, P

D t -. If time intervalN

nor between two adjacent moments of code change at the output of register 12 is equal to Q, then the difference of the compared input

frequencies fi and T2 can be found by the formula

I fi-f2 I 1 / QKP.

The change of the code at the output of register 12 is fixed with the help of register 13 and BSK 8. The pulse from the output of the FWI 6 delayed

on TV element 9 delay (2g), its front records the code produced by the ADC 11. into the register 12, and the code from the output of the latter - into the register 13, and then. reset the integrator 10 to its original state. Each time the status code changes, register 12 (2e) and register 13 (2g) will differ from each other during the interval riT2, where T2 is the period of the signal at the first input, which is registered by BSK 8.

The signal at its output (A & B) FKI 7 produces a pulse (2h), arriving at counter 4.

The measurement time is set by divider 3 frequencies. If it has a division coefficient of N, then the time of each measurement in the device is nNT. After that, the contents of counter 4 with the front of the DF 3 signal are rewritten to register 5, and counter 4 is zeroed. If during the time of the next measurement it was received from the FKI 7M pulses, then the frequency difference can be determined by the formula

45

- -; ЈЈ

or

M

I f 1 f2 „

f2nNKP

The relative measurement error due to the effect of quantization in the ADC is g 1 / nNKP.

Thus, the device, with the same relative measurement error as with the prototype, makes it possible to reduce the measurement time in the RC.

Claims (1)

Apparatus of the Invention A device for measuring a frequency difference, comprising a first frequency divider, the output of which is connected to an input of a time interval former, as well as a second frequency divider, a code comparison unit, a short pulse former and a counter, characterized in that in order to increase speed and extend the range the frequency difference to be measured, a frequency multiplier, an integrator, an analog-to-digital converter, a delay element, first, second and third registers are entered into it, with the output of the frequency multiplier Erez serially connected generator slots, an integrator, an analog-digital converter, first register, second register, -J-4JV 15 it 11 II I I I I I I I I I II II I I I M I I I 1 1 1 1 Tr-P rm l l 0 the code comparison unit, the short pulse driver and the counter are connected to the first inputs of the third register, the output of the first frequency divider is connected via the second frequency divider to the second inputs of the counter and the third register, the output of the time slot generator is connected to the second inputs of the integrator, the first and second registers and the output of the first register is connected to the second input of the Comparison Unit, and the output of the delay element is connected to the second input of the short pulse driver. P g l l