SU1607621A1 - Fixed memory matrix storage making method - Google Patents

Abstract

The invention relates to computing technology, in particular, to the technology of manufacturing semiconductor integrated circuits, and can be used to make a matrix storage device of an electrically reprogrammable permanent recording device. 1 of the invention is the acceleration of the speed of the matrix storage. The advantage of the matrix accumulator is the presence of regions of small width1, obtained without using a small design rate, and ensuring a small area of overlap of the projection of the diffusion region without using additional photolithographic operation with small dimensions. In addition, the size of the memory cell is reduced. 8 il. R

Description

The invention relates to computing technology, in particular, to the manufacturing technology of semiconductor integrated circuit chips No. 1, and may be; used to manufacture a matrix storage electrically reproducible read-only memory.

The aim of the invention is to improve the speed of the matrix drive.

The method is illustrated by the sequence of supports shown in Figs. 1-8, where the following conventions are used: by; forged substrate 1 of the first conductivity type, SL (1st 2 of silica and a layer of 3 nc silicon nitride, the first diffusion coating of the first type

conduction, the first dielectric layer 5 of silicon dioxide, the second diffusion region 6 of the first conductivity type, the second dielectric layer

7 of silicon dioxide, the first group is a wire of 1 p1X areas 8 of polysilicon, a third layer of dielectric 9, the second group is a wire of hdih areas 10 of polysilicon, a layer of 11 photoresist with holes, a third diffusion of the 12 region of the second type of conductivity, the fourth dielectric layer 13 made of phosphorus silicate insole, the third group of conductive regions 14, the fourth group of conductive regions 15

from polysilicon.

In the manufacture of a matrix accumulator, the first semiconductor substrate 1 is applied to the surface

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The conductance layers 2, 3, alloy the substrate 1 with an admixture to form the first diffusion layer 4 of the first conductivity type (Fig. 2).

HaHocfit layer 5 of silicon dioxide on the surface of a semiconductor grating 1. Apply a layer of 11 photoresist with holes-On the surface of layer 5 and 3 of silicon nitride, etch the first layer 5 through the holes of layer 11 to the surface of the semiconductor substrate 1 (fig.Z)

After a layer of photoresist 11 and layers 2, 3, the substrate 1 is doped with an impurity to form a second dmM Uznonnoy region b of the first conductivity type. The deposited layer of silicon dioxide 7 is deposited onto the surface of the semiconductor substrate 1j, a doped layer 8 of poly- is deposited; the straps on the surface 5, .7 form regions 8 in it when etching them, narrow regions 15 ( .4, section, FIG. 5 section (bb)

Narrow areas.15, located on the lateral surface of the layer 5 and the surface of the layer 7, are formed during the reactive ion etching of the layer 8 due to the greater thickness of this layer in the spots,

A third layer 9 is deposited on the surface of regions 8, layer 5 and substrate 1. A surface is attached to the surface of section 9 of the policremia (php.5, section A-A, BB), and a second group of regions is formed from it. 10 and group of areas 15,

The substrate 1 is doped with an impurity to form a third diffusion layer 12 of the second conductivity type (Fig. 7,: section G-D).

A layer 13 of phosphorosilicate CTLMuia is deposited on the surface of the regions 10, the semiconductor substrate 1, layer 5, is formed in the layer .13 of the aperture. A metallic layer is applied to the surface of the layer 13 and the semiconductor substrate J I to form in it a third, a group of regions 14 (FIG. 1.8),

Areas 8 are floating-op-Ti opai-M apog-p1nayuchichnyh .trans.zistorov, areas 15 - plates of capacitors, other plates - layer 12, about LPST15 10 control gates of memory of transistors and gateways of address BN-tramistors connected in series with the transistors, the layers 12 to which the regions .14 are connected are the drain of their transistors, the layer

5–12, located between regions 10, are the sources of address MOS transistors and the terminator bus of the matrix drive.

The operation of the matrix drive is closed to,. In the information reading mode, a low positive voltage of +5 V is supplied to the selected address polysilicon. The bus 10 is fed to the low-voltage positive voltage of the other 5, and the common diffusion bus 12 is supplied to the zero voltage. On zy- branes. bit metal tires

14, a low positive voltage of +1 V is applied, the others are zero. :

Under: by the action of these voltages, the address MLP transistors are selected. the rows are open. The scientific research institutes, the other addressed MDP-transistors of the Stores are in the closed state. If the threshold voltage of the selected storage transistor exceeds (does not exceed) the voltage on the address polysilicon bus 10, then it is in. the closed (open) state is .II, through its own, the open address IDP transistor, the metal discharge bus 14, the total diffusion t 12 does not leak (flow) current,

 which is equivalent to the zero (one-1) state. Through the rest of the discharge metal tires 14, the current does not flow due to the presence of zero. . nasch5 bride on address polysilicon -.

d) 10 or a metal mining mine 14.

The total simultaneous erasure of the information of the memory cell of the matrix storage device is carried out by applying a high positive pulse voltage (16 V, 1–3 s) to the general diffusion utmiy 12 at zero times. brides on targeted polysilicon tires 10 and bit metal tires 14,

Under the action of high voltages between the edge of the diffusion tire 12 and the protrusions of the polysilicon electrodes.

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 The charge of electrons through the second dielectric layer 7 of small thickness is removed from the polysilicon electrodes 8, as a result of which the threshold voltages of all I remember 1 P1x transistors

0

become negative, equivalent to a single state.

The advantage of the matrix accumulator is the presence of small width regions 15, obtained without using a small design form and providing a small overlap area of the projection of the diffusion region 10 without using an additional photolithographic operation with small dimensions. In addition, the storage cell size has been reduced in the drive.

Scope of the Invention A method of manufacturing a matrix storage device for a permanent storage device, comprising forming in the subsurface region a semiconductor substrate of the first type and conductivity of the first diffusion regions of the first type of conductivity, forming a first dielectric layer with holes arranged on the surface of the first diffusion regions. - formations, the formation in the near-surface region of a semiconductor substrate of the second diffusion region of the first type of conductivity, the forcing of the second dielectric layer located on the surface of the semiconductor substrate, the formation of the conductive regions of the first group of polysilicon located on the surface of the first and second dielectric layers

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Claims (1)

formula A storage device method for read-only memory, including the formation of a first type of semiconductor substrate in the near-surface region of the conductivity of the first diffusion regions of the first conductivity type, the formation of a first dielectric layer with holes located on the surface of the first diffusion regions ^{: the} formation of a semiconductor substrate in the surface region the second diffusion region of the first type of conductivity, the formation of a second dielectric layer located on the floor surface a conductive substrate, the formation of conductive regions of the first group of polysilicon located on the surfaces of the first and second layers of dielectrics " AT 5 I— —'- 4 - J || --- J ^r Ιίι'γ — ί! b ^ - t - 'i ---' “Ί Ί Ϊ -— 1 trick, formation of a third dielectric layer with holes located on the surfaces of the first, second dielectric layers and conductive regions of the first group, formation of conductive regions of the Second group located on the surface of the third dielectric layer, formation of “third diffusion regions of the second type conductivity in the surface region of the semiconductor substrate, the formation of a fourth dielectric layer with holes located on the surfaces of the third dielectric layer and the conductive region the second group, the formation of the conductive regions of the third group, located on the surfaces of the semiconductor substrate and the fourth dielectric layer, characterized in that, in order to increase the speed of the matrix drive, when conducting regions of the first group are formed by reactive ion etching, a conductive region is formed, located on the surface of the second dielectric layer and adjacent to the side surface of the first l dielectric layer, and when the conductive regions are formed, the second group is formed rovodyaschie fourth area groups • partially etching a conductive region adjacent to a side surface of the first dielectric layer.