SU1605302A1 - D.c. to d.c. voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in power supplies of electronic equipment, in particular for powering computer components. The purpose of the invention is to reduce the level of switching noise. The goal is achieved by the fact that comparators, AND gates, OR gates, and a current transformer are introduced into a converter containing a resonant inverter comprising Drossel, a capacitor, a transformer, and a current inductor and a choke. The output voltage of the converter is stabilized by changing the parameters of the resonant circuit by adjusting the inductance of the choke.

Description

The invention relates to electrical engineering and can be used in power supplies of electronic equipment, in particular for powering computer components.

The purpose of the invention is to reduce the level of switching noise.

1 shows a diagram of a converter; Fig. 2 shows a possible embodiment of the drossel; Fig. 3 shows the dependence of the inductance of the main winding of the throttles on the amperats of the control winding; 4 shows time diagrams of voltages and currents.

The constant-voltage-to-constant-voltage converter (Fig. 1) contains a push-pull, for example, a bridged series resonant inverter 1 comprising droplets 2 with a main coil 3 located on a ferromagnetic magnetic core 4, a capacitor 5, an output transformer 6, a rectifier 7, a load 8, the key elements 9–12 and reverse diodes 13–16. There is also a control block 17 comprising the pulse generator 18, the trigger 19, the AND 20 and 21 logic elements, the differential amplifier 22 and the reference voltage source 23,

The first 24 and second 25 comparators, the third 26 and fourth 27 AND gates, the first 28 and second 29 OR gates, and the current transformer 30 are included in the circuit. The choke 2 is provided with a control winding 31.

In a number of cases in the converter, it is advisable to use the protection unit 32 in the composition of the rectifier 33 and the comparator 34.

The Converter (figure 1) works as follows.

Upon receipt of the next positive start pulse E, g from the output of the generator 18, operating

about:

sd oo

ND

160

at a constant value of the period T g, const of the pulse, the trigger 19 is set to the state of a logical unit E. at the direct output and in the state of logical zero at the inverse output (FIGS. 4 a, 6, c). The positive voltages Ej at the output of the rectifier 33 and the inverting input of the comparator 34 under these conditions. less than the positive reference voltage Ejj of the source 23 at the non-inverting input of the comparator 34 and at the third inputs of the logic elements

magnetic circuit 4 and, as a consequence, the change in inductance L winding 3

Fig. 3 shows the experimentally obtained dependence of the inductance Lj of the winding 3 on the ampere-turns of the winding 31, obtained in a case of using a toroidal-armored detachable magnetic conductor with an outer diameter of 21 mm and a height of 14 mm from a 1500NM ferrite. The winding 3 so-g holds 20 turns, and the winding 31 - 12 turns.

Thus, according to FIG. 3 with

20, 21, 26 and 27 there is a voltage 15 using a control winding 31,

logical unit.

3, the result of all three inputs of the logical element And 26 is the voltage of the logical unit (Fig, 4 g). As a result, the momentum E ,; 20 from the output element 26 through the element OR 28 enters the gates of the key elements in the form of field-effect transistors 10 and 11 and unlocks them. The logical elements And 21 and 27 remain locked- ,. 25 1, because the voltage from the inverse of the trigger 19, arriving at the south. first inputs: has a logical zero level. As a result, at the output of the -logical element .OR 29, the voltage has a logic level of zero and transistors 9 and 12 remain locked. At the same time, transistors 10 and 11, the primary winding of transformer b, capacitor 5, current transformer 30 and main winding 3 begin to flow through current I-form the positive half-cycle of the sinusoid (FIG. 4 e). The T / 2 capacity of this half-period is determined by the serial parameters A resonant circuit formed by the inductance Lg of the winding 3 droplets 2 and the capacitance C 5 of the capacitor 5, magnetically containing, for example, 2000 turns, can provide an almost twofold change in inductance Lj (395 - 220 μH), if the current through the winding 31 bu is varied within the O - PCA. Such a current may well be provided by a differential amplifier 22, performed, for example, on an operational amplifier.

At the same time, a positive pulse appears at the output of the current transformer 30, which coincides in shape with the current half-period Ij, so a positive pulse 3,4 / incoming to the second input of the logic element I 2 appears at the output of the comparator 24 (Fig. 4). g) This pulse then goes through the element lOTi 28 to the gates of transistors 11 and 10. They are kept with the action of the pulse Eg in the open state after the start of the starting pulses and Egg until the current Ij, having passed through the maximum, vanishes (Fig , 4 a, g, e, g).

40

At this point, the pulse E is finished and the transistors 10 and 11 are locked.

When the next impulse is launched. After a time T longer than the duration T / 2, the semi-conductor 4 throttle 2 has a toroidal current Ij, trigger 19 re-armor form (Fig. 2) and is in a state where the voltage is

E,

The inner annular cavity of the toroid is the main winding 3, and the control winding 31 is located around the circumference of the outer surface of the toroid. The magnetic fields of the windings 3 and 31 are orthogonal (i.e., perpendicular to each other), which provides virtually no connection between the windings in alternating current,

A change in direct current through the winding 31 causes a corresponding change in magnetic insight.

50

 19 g ° inverse output acquires a level of logical unity; s (figure 4 a, b, e). At the same time, the logical element AND 27 is unlocked, and through it and the element 29, a pulse 27 is supplied to the gates of transistors 9 and 12 (FIG. 4d). transistor 12; its direction back to the direction in the previous cycle (figure 4e), Elements 26 and 28, as well as transistor0 5

containing, for example, 2000 turns, it is possible to provide an almost twofold change in the inductance Lj (395 - 220 µH) if the current through the winding 31 changes within O - 3 mA. Such a current may well provide a differential amplifier 22, made for example on an operational amplifier.

At the same time, a positive pulse appears at the output of the current transformer 30, which coincides in shape with the current half-period Ij, so a positive pulse 3.4 appears at the output of the comparator 24 / arriving at the second input of the logic element AND 20 (FIG. 4) ). This pulse then goes through the element lOTi 28 to the gates of transistors 11 and 10. They are kept under the action of the pulse Eg in the open state after the start of the starting pulses and Egg until the current Ij passes through the maximum and vanishes. (Fig, 4 a, g, e, g).

0

At this point, the pulse E is finished and the transistors 10 and 11 are locked.

Upon receipt of the next trigger pulse. After a time T longer than the duration T / 2 of the current half-period Ij, the trigger 19 is shifted to the state when the voltage is

E,

0

 19 g ° inverse output acquires a level of logical unity; s (figure 4 a, b, e). In this case, the logical element AND 27 is unlocked and, through it and the element 29, a pulse 27 is supplied to the gates of transistors 9 and 12 (FIG. 4e). Now the current Ij begins to flow through the transistor 9, the winding 3 of the throttle 2, the current transformer 30, the primary winding of the transformer 6 and the transistor 12; its direction back to the direction in the previous cycle (figure 4e), Elements 26 and 28, as well as transistor 16053026

The current inducts 1z and as a result, to a decrease in 1s.r and output voltages

ka Ij, arriving at the inverting E, This process will occur the input of the comparator 25, at its output

Pins 10 and 1 remain locked. Under the influence of a negative impulse

a positive pulse E appears under the action of which the logical element I 21 is unlocked (Fig. 4d). The pulse E 22 through the logic elements 21 and 29 is supplied to the gates of the transistors 9 and 12, whereby they are held in the open state after the start of the trigger pulses and as described above. Transistors 9 and 12 remain in the conducting state similarly to the previous one for the duration of the negative half-cycle of current 1 and pulse E 25 after which they are turned off (Figs. 4e, 3e).

So, the switching on and off of elements (transistors 10, 11 and 9, 12) occurs at the moments when the current Ij crosses through zero, which allows to reduce the level of switching noise to the maximum. Is-

as long as the voltage E-, again

7

before

 will not be equal to the specified nominal. The switching process of transistors 9-12 will still occur at the moments of the current Ij passing through zero. Q Thus, the process of stabilizing the output voltage will not be accompanied by an increase in the level of switching noise.

When a current overload occurs, the voltage at the output of the current transformer 30 and, therefore, at the output of the rectifier 33 and and; and the inverting input of the comparator 34 becomes greater than the reference voltage of the source 23 at the non-inverting input. As a result, the voltage at the output of the comparator 34 and at all the third inputs of the logic elements AND 20,21,26 and 27 goes to zero. Therefore, when a current overload occurs, the voltage at the output of the current transformer 30 and, therefore, at the output of rectifier 33 and and, and the inverting input of comparator 34 becomes greater than the reference voltage of source 20 at the non-inverting input. As a result, the voltage at the output of the comparator 34 and at all the third inputs of the logic elements AND 20,21,26 and 27 goes to zero. Therefore, the insertion of through currents through transistor-25 logic elements of the locking devices 9-12 in this case is ensured. As a result, goes into lock

thanks to .11

guaranteed

pauses at observance of the temporary ratio T13 T / 2.

The average value of 1sr current Ic (and, consequently, the voltage E at the outflow of the rectifier 7, i.e., the voltage at the output of the converter) is determined from the ratio

thirty

This state and key elements 9–12. As a result, the flow of current Ij is stopped, and this ensures protection of the nvertor. The reclosing takes place automatically after the filter capacity in rectifier 33 is discharged. To protect the inverter elements from overvoltages that may occur on the capacitor 5 during current overloads, a double-sided 35 amplitude limiter on zener diodes can be used.

I - G.

 -, - S1 18 J

sinQdt

1zT

f g

U 1

18

where Q - L5Cj - circular frequency.

From this it follows that the value of 1cp linearly depends, with const, on the duration T / 2 of the half-periods of the current Ij, which in turn depends on the inductance Lj of the winding 3 droplets 2,

Output Voltage Stabilization

40

This state and the key elements 9-12. As a result, the flow of the current Ij is stopped, and this ensures protection of the nvertor. The reclosing takes place automatically after the filter capacity in rectifier 33 is discharged. To protect the inverter elements from overvoltages that may occur on the capacitor 5 during current overloads, a double-sided 35 amplitude limiter on zener diodes can be used.

Claims (1)

Formula invented and. The DC / DC converter, which contains a push-pull resonant inverter comprising throttle, capacitor, output converter, is implemented by a barely 45 transformer, rectifier, and in the same way. The voltage is E-. is compared in the differential amplifier 22 with the reference voltage from the source 23. The output voltage of the amplifier 22 thus contains information on the deviation of the magnitude of Ey from the specified nominal value. If, - for example, the voltage E. begins to increase, then the voltage at the output of the amplifier 22 also begins to increase, and the current through the winding 31 increases. According to the graph of FIG. 3, the inductance L 3 R will decrease, which will decrease the duration T / 2 of the half-point elements, as well as the control unit consisting of the pulse generator, the trigger, the two logical elements And the differential y force, 50 to one input of which the output of the rectifier is connected, and to another input - the source of the reference voltage, to the output of the pulse generator the input of the trigger is connected, the forward and inverse outputs of which are connected to the first inputs of the first and second logic elements, respectively; and so that, in order to reduce the level of interference. E, This process will occur as long as the voltage E-, again 7 before  will not be equal to the specified nominal. The switching process of transistors 9-12 will still occur at the moments of the current Ij passing through zero. Q Thus, the process of stabilizing the output voltage will not be accompanied by an increase in the level of switching noise. When a current overload occurs, the voltage at the output of the current transformer 30 and, therefore, at the output of the rectifier 33 and and; and the inverting input of the comparator 34 becomes greater than the reference voltage of the source 23 at the non-inverting input. As a result, the voltage at the output of the comparator 34 and at all the third inputs of the logic elements AND 20,21,26 and 27 goes to zero. Therefore, these logical elements are locked. As a result, goes into lock thirty 35 40 This state and the key elements 9-12. As a result, the flow of the current Ij is stopped, and this ensures protection of the nvertor. The reclosing takes place automatically after the filter capacitance in rectifier 33 is discharged. To protect the inverter elements from overvoltages that may occur on the capacitor 5 during current overloads, a double-sided 35 amplitude limiter on the zener diodes can be used. Formula invented and. DC / DC converter containing a push-pull resonant inverter consisting of a drosel, a capacitor, an output transformer, a rectifier, and key elements, as well as a control unit comprising a pulse generator, a trigger, two logic elements AND, and a differential force, k 50 to one input of which the output of the rectifier is connected, and to another input - the source of the reference voltage, to the output of the pulse generator the input of the trigger is connected, the forward and inverse outputs of which are connected to the first inputs of the first and second logic elements, respectively; and so that, in order to reduce the level of interference. The first and second comparators, the third and fourth logic elements H, as well as the first and second logic elements ILR1 and the current transformer are introduced into it, and the choke is equipped with a control winding located on the magnetic core in a plane perpendicular to the plane of the main winding, moreover, the control winding is connected to the output of the differential amplifier, the primary winding of the current transformer is connected in series with the main winding of the choke, and to the first output of the secondary winding of the current transformer, the second terminal of which is connected to the common bus, connected non-inverting respectively. and inverting the inputs of the first and second comparators, inverting and non-inverting inputs which are connected to the common bus, the outputs of said comparators are connected to the second inputs of the first and second logic elements AND, the outputs of which are connected to the first inputs of the first and second logic elements OR, respectively, of which are connected to the control inputs of the corresponding key. , the output of the pulse generator is connected to interconnected first inputs of the third and fourth logical elements, respectively, the second inputs of which are connected respectively to the direct and inv rsnomu outputs of the flip-flop, the outputs of the third and fourth AND gates are connected to second inputs of the first and second OR gates. 200 0.5 FIG. five Figg sci