SU1599797A1 - Device for measuring value of sync window reserve in case of phase-manipulated signals - Google Patents

Abstract

The invention relates to measuring systems, in particular, is intended to measure the value of the synchronization window margin in floppy disk drives with phase-shifted signals taken from the output of a controlled drive. The purpose of the invention is to improve the accuracy and automation of measurements in the analysis of the operation of drives. This goal is achieved by introducing a decoder, two multiplexers, a trigger and a counter, connected in such a way that it allows you to form certain temporary gates in the required place and automatically control the duration of these gates. Changing the duration of the synchronization window allows you to control the quality characteristics of the storage device. The device contains a reference generator 1, first 2, second 3, third 4 and fourth 5 counters, first 6, second 7, third 8 multiplexers, adder 9, decoder 10, delay elements 11, 12, two terminals 13 and 13 ¹ for connecting the subject the quadrupole, the first indicator 14, RS-trigger 15, the first 16 and the second 17 elements And, the second indicator 18. 2 Il.

Description

FIG. one

3159

The invention relates to a technique in | belt and phase measurements, and is intended for measuring parameters of four polar cells with phase information coding.

The purpose of the invention is to increase the measurement of NUCLE

Fig, 1 shows a block diagram of the proposed device; on . Fig, 2 - time diagrams of work.

The device contains the reference generator T | 0p 1, counters 2-5, multiplexers 6-8, adder 9, decoder 10, elen-delays 11 and 12, two terminals 13 J and | 13 for connecting the test quadrupole, indicator 14, trigger 15, two elements 16 and 17, and a second indicator 18,

Signals generated by master

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The output of the reference generator 1 is connected by a generator (fig. 2a), is fed to

thirty

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Nin with the counting input of the counter 2, the information outputs of which are connected to the control inputs of multiplex 8 and the decoder 10, the outputs of which are connected to the information inputs of multiplexers 6 and 7, the outputs of which are respectively connected to the inputs of the RS trigger 15 The output of the first counter 2 is connected to the counting input. counter 3, the information codes of which are connected to the control inputs of the multiplexers 6 and 7, the second and the 18, the input of the counter 3 is connected to the input of the first indicator 14 non- P (directly and through the element 12 for the R-inputs of the third 4 and the fourth in the 5 counters, the informational B ||) inputs of which are connected to the inputs of the adder 9, the output of which is connected to the indicator 14, the output of the reference generator 1 and the first inputs of the elements 16 and 17, the outputs of which are respectively connected to the inputs of counters 4 and 5, the output of the multiplexer 8 is connected to p pin 13 for connecting the tested quadrupole 19 and through the delay element 11 is connected to the second input of the first element 16 and the second input of the second element 17 is connected to the output of the RS-trigger, gfra 15, and the third input of the element 17 is connected to the second terminal 13 for sub, (1 points of the studied quadrupole.

In the initial state, all the counters of the device are reset to zero. Counter 2 and multiplexer 8 form a master oscillator that generates a signal of the desired shape, which is input to the test input of the quadrupole 19 under study, the output of which (Fig. 2b) is distorted by time. These signals periodically arrive at the input element And 17, to the other inputs of the same element receives a signal from the reference generator 1 and a variable-duration signal temporary gate. If the duration of the temporary gate is longer than the duration of the signal from the quadrupole or equal to it, then the numbers (codes) counted by the counters 4 and 5 are equal and at the output of the adder 9 the signal differs little from the zero value. With the appearance of discrepancies in time, the counters should differ significantly, and the differences depend on fluctuations along the time axis of the signal at the output of the quadrupole. Connecting the outputs of the decoder 10 through multiplexers 6 and 7 to the RS-flip-flop 15, you can connect the next two outputs of the decoder to get the minimum temporary gate, and by connecting two extreme leads of the same decoder, get the maximum value of the same temporary gate. Thus, the signal at the input of the counter 3, one can discretely change from a higher value to a smaller amount of the synchronization window margin (temporary gate 2c) to the appearance on the indicator 14 of information about the presence of its losses in the monitored signal path

A properly working quadrupole has a small fluctuation of phases and therefore the signal from it passes without distortion through the temporary gate of a small

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th quadrupole, the signal processing time is determined by the capacity of the counter 2 at each of the selected gate lengths. Delay element 11 compensates for the time incursions occurring in the circuit, delay element 12 delays the reset of counters before recording information on indicator 14. Counter 3, connected to the control inputs of multiplexers 6 and 7, forms a temporary gate of variable duration with each switch.

A counter 4 is connected to an adder 9 with inverse outputs.

The device works as follows.

Signals generated by master

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generator (figa), arrive at

duration (approximately 400 not). A poorly operating quadrupole 19 does not fit into these time constraints. Changing the duration of the temporary gate, using the counter 3 and multiplexers 6 and 7, according to the time of the loss of information, judge the quality of manufacture (FIG. 2 g, d) of the quadrupole 19. In the absence of loss of information, the information accumulated during the measurement time in the counters 4 and 5 is equal and, at the output of the adder 9 operating in the mode of subtracting codes, numerical values are obtained on the indicator 14, which are related to the error in measuring the Sne meters more than 13 units). In the event of a loss of information, this numerical value is hundreds or more units, which makes it possible to judge with confidence the quality of the quadrupole 19 under study (fig2e, g).

Claims (1)

Invention Formula A device for measuring the magnitude of the margin of the synchronization window with phase-mapped signals, which contains two terminals for connecting the tested quadrupole, an adder, an indicator, a reference oscillator and a delay element, characterized in that, in order to improve the measurement accuracy, a second delay element is introduced into it, a counter, three multiplexers, a trigger, a second indicator, two elements And, a decoder, while the output of the reference generator is connected to the counting input of the first counter, the first input of the first element And, the first Exit first counter connected to the decoder inputs, the lower and upper outputs of which are respectively connected to the information inputs of the first and second multiplexers, the outputs of which are respectively connected to the inputs of the RS flip-flop, the output of which is connected to the second input of the first element I, the second output of the first counter Q ka is connected to the counting input of the second counter whose information outputs are connected to the control inputs of the first and second multiplexers, the first outputs of the first counter are also connected to the control inputs The third multiplexer, whose code through the terminals for connecting the studied quadrupole is connected to the third input of the first element And, the first input of which is connected to the first input of the second element And, the second input of which through the first delay element is connected to the output of the third multiplexer, the outputs of the first and second 25 elements And respectively connected to the counting inputs of the third and fourth meters, the outputs of which are connected to the inputs of the adder, the outputs of which through the first indicator are connected with the first information code of the device, the second output of which is combined with the information outputs of the second counter and the inputs of the second indicator, the second output of the first counter je is directly connected to the clock input of the first indicator, and through the second delay element m with the inputs R of the third and fourth counters, the first information input of the third 40 multiplexer is connected to the signal source of a logical unit. T & see sienna / Lj Hcxodh Siena / with Kenya lawsuit 3 yes 7th condition Predefined condition ..... .... window Juil J1il J1il Signal / fb / at cvemvufca input 3 yes f Sensery II 9th whether Signals on the cvemw / caS bypass F 0 FIG. 2 Cumulative / ieHHoe value on c (/ / mma torr Indicator readings