SU1598147A1 - Commutator - Google Patents

Abstract

The invention relates to instrumentation engineering and can be used in switching devices of automated measuring systems (AIS). The switch contains two registers 4 and 5, a block of 6 And elements, a block of 7 electronic keys, a block of 8 current sensors, a block of 9 relays, a block of 11 current comparators, a D-flip-flop 14 and the corresponding buses. The purpose of the invention is to increase reliability - by preventing improper commutation when there are faults in the control circuit of electromagnetic relays by using D-flip-flop 14, the output signal of which blocks the passage of information signals to the inputs of the electronic switches 7 through the 6 elements And the account of providing the possibility of identifying the faulty control circuits by the output signals of the third register 16, the information outputs of which receive the output signals of the block 12 note, and the clock input is a delayed "write" signal. 1 il.

Description

The invention relates to instrumentation engineering and can be used in switching devices of automated measuring systems (AI C).

In order to increase the reliability of measurement results and eliminate the possibility of disabling AIS devices in AIS switching devices, self-control is introduced.

The purpose of the invention is to improve the reliability of the device by preventing incorrect commutation in case of malfunctions in the control circuit of the electromagnetic relay by prohibiting the switching on of the relay, as well as by providing the possibility of identifying the control circuits in which the failure occurred.

The drawing shows the block diagram of the device.

The switchboard contains input data bus 1, input bus 2 records, input bus 3 presets, first register 4, second register 5, block 6 And elements, block

7 electronic switches, a block of 8 current sensors, a block of 9 relays, a power bus 10, a block of 11 current comparators, a unit 12 of the same comparison, an element OR 13, a D-trigger 14, a block

15delays, third register 16, input bus 17 Disabling lockout, output bus 18 Failure of the initial state, output bus 19 Failure, data output bus 20, the input buses connected to the corresponding inputs of the first register, the key block is connected to the current sensor block connected to the current comparator unit, the outputs of which are connected to the second inputs of the bitwise comparison unit.

The switch works as follows.

In the initial state, after the preset signal is applied to the preset input bus, the first 4, second 5 and third

The 16 registers, as well as the D-flip-flop 14, are in the initial zero state, the Electronic key block 7, respectively, the block 11, and also the relay block 9 are in the off state. Consequently, during normal operation of the circuit, the outputs of the elements of block 12 of one-way comparison and, accordingly, the output of the element OR 13 will be signals corresponding to logical O, if due to malfunctions in the relay control circuit any electronic key is turned on, the corresponding output block 12 of bitwise comparison and, respectively, at the output of the element OR 13 and the output bus 18 Failure of the initial state is allowed by the signal corresponding to logical 1, i.e. a failure of the original state is detected.

To switch on any relays in block 9 of the relay, the corresponding encoded signal 5 (in the bits corresponding to the activated relay, the signal corresponds to the logical G) is fed to the input data bus 1, and the accompanying clock signal to the input bus 2 records. With 10 of this, the coded signal corresponding to the switching on of the specified relays is recorded in the first 4 and second 5 registers, which causes the inclusion of the corresponding electronic switches of the block 7 and, accordingly, the current comparators of the block 11. At the first inputs, as well as with some delay defined the inertia of the circuit, the block of 7 electronic switches, the block of 8 current sensors, the block of 9 relays (mainly determined by the used relays), the second inputs of block 12 of the one time comparison receive signals corresponding to the input coded signal and switch on relay, i.e. triggered comparators 25 of block 11. When they coincide, all outputs of block 12 of bitwise comparison, as well as the output of the IL AND 13 element, store signals corresponding to logical O. The recording signal, passed through block 15 of delay, goes to clock inputs the third register 16 and the trigger 14, ensuring the latching of the output signals of the unit 12 of bitwise comparison and the element OR 13. In this case, the delay unit 15 compensates 35 for the inertia of the signal to the information inputs of the third register 16 and the trigger 14.

The operation current of the current comparators is chosen so that their 40 operation occurs at a current less than the relay operation current (almost 0.5-0.7 operation current), and the delay time of the delay unit 15 is slightly longer than the current rise time in circuit 5 of unit 8 current sensors to the magnitude of the current response of the current comparators (determined by the relays used).

In the event of a fault in the circuit -. nor any relay, the output signal of the block of 11 clock comparators will not correspond to the input code (output signal of the second register 5). At the same time, the corresponding output of block 12 is parallel comparing and, accordingly, at the output of the element OR 1-3, a signal corresponding to logic 1 appears. This will be fixed when the recording signal arrives at the clock inputs of the third register 16 which is delayed in block 15. and trigger 14, low level signal with

the inverse output of D-flip-flop 14 will prohibit the switching on of the relay, entering the second inputs of block 6 of the elements I, the signal corresponding to the logic G, from the direct output of the D-flip-flop will inform the external device about the occurrence of a fault via the output bus 19 Failure, using the output code of the third Register 16, which is fed to the external data bus 20, identifies a faulty switch circuit (a faulty circuit corresponds to a logical 1 signal).

The device is practically implemented in the development of AIS, to check the parameters of pulse generators, in the measuring switch unit, the software control of the switch unit is carried out on the microelectronics Electronics 60 through the unified instrument interface of the CPC.

In the practical implementation of the switch, the first 4, second 5, and third 16 registers are made on a four-bit register microcircuit.

The K155TM2 trigger is used as the D-grigger 14.

Unit 7 of electronic keys is implemented on transistors of the 1НТ251 transistor matrix according to the electronic key scheme with a common emitter. In block 6, elements AND were used elements 2 AND-NOT with an open collector K155LA8.

Block 8 of current sensors and block 11 are made on optocouplers 249ЛП 16. Block 12 of bitwise comparison is implemented on the elements exclusive OR of K155LP5 microcircuits. and block 15 of the delay on the one-shot 155AGS,

The second preset input to D-flip-flop 14 is provided by the use of an additional element 2 OR in the preset circuit.

Claims (1)

Invention Formula A switch containing an input data bus, an input write bus, an input 5 10 15 20 five 0 five 0 five preset bus, first register, dongle unit, current sensor unit, relay unit, power bus, current comparators unit, output bus Initial state failure and output bus Failure, the input data bus, input write bus and preset input bus are connected to the corresponding the inputs of the first register, the electronic key block is connected to a series-connected power bus, a relay block and a current sensor block, which is connected to the input of a current comparators block, so that, in order to increase the reliability , a second register, an AND block, a one-bit comparison block, an OR element, a D-trigger, a delay block, a third register, an input bus Disable lock, and an output data bus are additionally entered into the device, and the data inputs, records and presets of the second register are connected to the corresponding inputs of the first register, the outputs of which are connected to the first inputs of the block of elements And, the second inputs of which are connected to the inverse output of the D-flip-flop, and the outputs to the inputs of the block of electronic keys, the outputs of the second register are connected to The first inputs of a one-bit comparison unit, the second inputs of which are connected to the outputs of the current comparator unit, and the outputs with the corresponding inputs of the third register and the OR element. the output of which is connected to the output bus Failure of the initial state and the information input of the D-flip-flop, the clock input of which is connected to the clock input of the third register and the output of the delay unit, the input of which is connected to the input bus of the recording, the input bus of the preset connected to the inputs of the 3rd register of the third register and D -trigger, the direct output of which is connected to the output bus Failure, and the outputs of the third register are connected to the output data bus, the second input of the D-flip-flop preset is connected to the input bus Disable lock.