SU1597770A1 - Apparatus for checking insulation resistance - Google Patents

Abstract

The invention relates to electrical measuring equipment and is intended to automatically monitor the state of isolation of objects containing a large number of electrically disconnected circuits, shunted by capacitors. The purpose of the invention is to improve the noise immunity. The signal from the zero reset bus 28 resets the counter of the switching unit 5. The test circuits 3.1-3.K of the control object 2 are disconnected from the comparison block 9. Key circuit 22 is reset, de-energized relay 7 with normally closed contacting groups 6, 10, 13 and 16. A signal from the trigger bus 29 connected to the first input of the element OR 19 appears at its output a pulse signal arriving at the input of block 20 delays, as well as to the (K + 1) -th control input of the switching unit 5. The test circuit 3.1 is connected to the first input of the comparison block 9 using one of the terminals 1.1-1.K, and the normally closed contact capacitor 4.1 is shunted Groups 6, 10, 13 and 16 relays 7 provide a connection to you ode source 14 voltage measuring low impedance voltage divider formed by the low-resistance resistors 8 and 11 and lower shoulder divider formed by resistor 8, to the body under study shunts circuit 3.1. Having passed through the NOT element 30, the signal also zeroed the trigger 26, which prepares the AND element 18 for passing signals from the output of the comparator block 9. The device also contains the mastering device 25 for holding time, the source 17 of the reference voltage, the decoder 34, the alarm unit 35, the signal inductors 31 and 32. 8 Il.

Description

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on a large capacitor capacitance A.1, and normally closed contact groups 6, 10, 13, and 16 relays 7 provide for connection to the output of source 14 of measuring voltage a low-resistance voltage divider formed by low-resistance resistors 8 and 1.1, and the lower arm of the divider formed by resistor 8, shunts to the test case

chain 3.1. Having passed through the NOT element 30, the signal also zeroed the trigger 26, which prepares the AND element 18 for passing signals from the output of the comparator block 9. The device also contains a master time master 25, a voltage source 17, a decoder 34, a block. 35 alarms, signal inductors 31 and 32. 8 Il.

The invention relates to electrical measuring equipment and is intended to automatically monitor the state of isolation of objects containing a large number of electrically disconnected circuits shunted by capacitors.

The purpose of the invention is to increase the containment.

Figure 1 shows a block diagram of an insulation resistance monitoring device; Fig. 2 is a functional block diagram comparison; on fig.Z - functional diagram of the switching unit; figure 4 - the functional scheme of the key scheme; FIG. 5 is a functional diagram of a time master; figure 6 is a functional diagram of the delay unit; figure 7 - timing diagrams of the device and its main nodes; Fig. 8 is a diagram illustrating the path of the leakage current from the source of the primary cell.

The insulation resistance monitoring device contains terminals 1.1-1.K. For connecting the control object 2, containing To the tested 3.1-K circuits, shunted by capacitors 4.1-4.K, respectively. The terminals 1.1-1.K for connecting the control object 2 are connected to the corresponding To inputs of the switching unit 5, the first (signal) output of which is connected through a serially closed contact group 6 of relay 7 and a low-resistance resistor 8 connected to a common bus. The first output of the switching unit is also connected to the first input of the comparison unit 9 and through the serially connected normally closed contact group 10 and the relay 7 and the low-resistance resistor 11 to the second input of the comparison unit 9. Second entrance

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Comparison unit 9 is connected to the common busbar via a timing capacitor 12, and through the normally closed contact group 13 of relay 7 is connected to the positive source of the measuring voltage source 14, the third input of the comparator unit 9 is connected via the clock capacitor 15 to a common busbar. group 16 relay 7 - with the positive pole of the source 17 of the reference voltage. Negative poles of voltage sources 14 and 17 are connected to a common bus, the output of comparison unit 9 is connected to the first input of an AND 18 element, the output of which is connected to the second input of an OR 19 element, whose output is connected to (K + 1) -th (control) the input of the switching unit 5, the input of the delay unit 20 and the second input 21 of the key circuit 22, the first input 23 of which is connected to the output of the delay block 20, the first output 24 of the key circuit 22 of the circuit 22 through the setting device 25 of the time delay connected to the setup S input RS-trig - Hera 26, the second output 27 of the key circuit 22 is connected to. the first output of the winding of the relay 7, the second output of which is connected to the common bus. The zeroing bus 28 is connected to the (K + 2) -th input (zero setting) of the switching unit 5 and the third input (zero setting) of the key circuit 22. The start bus 29 is connected to the first input of the OR element 19, and through the HE 30 element to the R- the input of the RS flip-flop 26. The inverse Q output of the flip-flop 26 is connected to the second input of the element I 18 and to the first output of the signal lamp 3t, the direct Q output of the trigger 26 is connected to the first output of the signal lamp 32, the second outputs of the signal lights are connected to the positive bus

33 food. M information inputs of the decoder 34 are connected to the corresponding M information outputs of the switching unit 5, and N outputs of the decoder 34 are connected to the corresponding N inputs of the signaling unit 35.

Comparison unit 9 (FIG. 2) contains a comparator 36 with high-resistance resistors 37 and 38 at the inputs. A resistor 39 is used as the load,

The switching unit 5 (FIG. 3) contains the element OR 40, the elements NOT 41 and 42, the one-shot 43, the binary-decimal counter 44 with the decoder 45 of the binary-decimal code connected to the output to the decimal code having (L + 1) outputs 43.1 - 45 (L + 1).

The L outputs of the decoder 45 are connected to the first terminals of the windings of the relay 46, the second terminals of which are connected to the positive power rail. The last (L + 1) -th output of the decoder 45 is connected through the element NOT 41 to the first input of the element OR 40, the second input of which is connected to the (K + 2) -th input (zero setting) of the switching unit 5, and the output through the one-shot 43 is connected with a counter input terminal 44, the counting C input of which is connected to (K + DM (control) input of the switching unit 5 via the second element NO 42. The switching contacts of each relay 46, connected together, form the signal output of the switching unit 5, and contacts - inputs from 1 to K. Outputs of the binary-decimal circuit In addition, information outputs from 1 to M of the switching unit 5 form. The single-oscillator 43 is designed to generate a zero-level impulse of a logical 1 of a predetermined duration from signals received either from the (K + 2) -th input (zero setting) of the switching unit 5, or from (L + 1) -ro output of the decoder 45 through the first element NOT 41. The decoder 45 converts the binary-decimal code of the counter 44 into the ten code of the type running zero.

The key circuit 22 (FIG. 4) contains the HE elements 47 and 48, the RS flip-flop 49, the transistors 50 and 51, the resistors 52-54, providing the specified modes of operation of the transistors, the damping diode 55, the OR element 56, the first input of which is the input 21 key schemes 22,

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the second is the third input (zero setting) of the key circuit 22, and the output through the HE 47 element is connected to the R input of the iRS trigger 49, the installation S input of which through the HE 48 element is connected to the first input 23 of the key circuit 22. Base transistor 50 through a resistor 52 is connected to the direct Q-output of RS-flip-flop 49, the collector of transistor 50 is the first output 24 of the key circuit 22, and the collector of the transistor 51 is the second output 27 of the key circuit 22. Time master 25 (Figure 5 ) contains the element HE 57, a one-shot 58 with external time driver ratios 59 and a cond The sensor 60, the one-shot 61 with external time master resistor 62 and a capacitor 63.

The delay unit 20 (FIG. 6) contains a one-shot 64 with an external time setting resistor 65 and a capacitor 66, a one-shot 67 with an external time setting resistor 68 and a capacitor 69.

The insulation resistance monitoring device operates as follows.

After the signal is sent to the null bus 28, the counter 44 of the switching unit 5 is zeroed out, at the outputs 45.1- 45. (L + 1) of the decoder 45 there is a level 1 logical signal, all relays 46 are de-energized and their normally open contacts are 46.2-46 L do not connect any of the tested circuits 3.1-3. To object 2 countershl to the first input of block 9 of the comparison. In addition, the keypad 22 on the third input (zero setting) is zeroed, ensuring the triggering of the RS flip-flop

49 in such a state when on its direct Q output level signal O. In this case, the transistors

The 50 and 51 key circuits 22 will be closed, the relay 7 is de-energized, and the first output 24 of the key circuit 22 will have a logic level signal 1. With the de-energized relay 7, the outputs of sources 14 and 17 of the measuring and reference voltages will be connected to the corresponding capacitors 12 and 15 which in the period of the presence of normally closed contact groups of the relay is charged to the magnitude of the voltages of these sources 14 and 17.

After giving the signal Start to: start bus 29, to the first input

element ISH1 19, in its code (FIG. 7, a pulse signal of logic level 1 appears with a duration determined by the time of the start signal, which is fed to the input of the delay unit 20, and also to (K + 1) (control) input switching unit 5 and then through the associated element HE 42 - to the countable C-input of the counter 44. As a result of the leading edge of this trigger pulse, the first input 45.1 of the decoder 45 generates a signal of the O level, providing the relay 46.1 (Fig.7l) and the connection to the first input of block 9 compare neither the circuit 3.1 under investigation, the capacitor 4.1, which is shrouded by a large capacitance 4.1. In this case, normally closed contact groups 10, 13 and 16. Relays 7, fused in the initial state, as shown in Fig. 1, provide a connection to the source output 14 of the measuring voltage of the low-resistance I divider, the voltage formed by the low-resistance resistors 8 and 11, the lower shoulder of the divider (resistor 8) bypasses the test circuit 3.1 to the case. As a result, an accelerated charge of the capacitor 4.1 capacitance, shunting the circuit under study 3.1, through a low-resistance resistor 11, occurs.

In addition, the Start signal, the passage through the NOT 30 element, wrapped the RS flip-flop 26, which by its output signal of the logic level 1 at the inverse Q output (fig.7g) prepares the And 18 element to pass signals from the output block 9 comparison.

The charge of the shunt capacitor 4.1 occurs up to the voltage value (fig.7p), determined by the low impedance voltage divider and corresponding to a value less than the reference voltage (by the absolute error of the device). The reference voltage is applied to the third input of the comparator unit and the inverted-in1-th 1st input of the comparator 36.

After a short time set in delay unit 20 (FIG. 7z), during which the accelerated charge of the shunt capacitor 4.1 is fully charged, a pulse signal of logic level 1 is generated at the output of delay unit 20 (FIG. 47i), which is

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stumbles on the first input 23 of the key circuit 22. This positive pulse signal, having passed through the element 48, provides for the RS-flip-flop 49 to roll over in the key circuit 22 in such a way that a logic level 1 signal appears at its output (FIG. ), providing the operation of the transistor 50 and 51 of the key circuit 22. As a result of the opening of the transistor 51, the relay 7 is triggered. In this case, all four normally closed contact groups 6, 10, 13 and 16 of the relay 7 open, as a result of which the second and third inputs of the block 9 comparisons are turned off the source outputs measurement 14 and reference voltage 17, but the indicated inputs of the comparison unit 9 remain under the voltage of charged timing capacitors 12 and 15. In addition, due to the opening of the normally closed contact groups 6 and 10 of the relay 7, the control object 2 is disconnected from the resistance of the low-resistance resistor voltage divider and the circuit 3.1 under study is provided for establishing the actual voltage in it by means of the dose of the shunt capacitor 4.1 through the high resistance resistor 37 of the block 9 corresponding to the real value of insulation (fig.7p). Opening the transistor 50 in the 1-chip circuit 22 at its first output 24 (connected to the collector of the transistor 50) results in a logic level O signal (FIG. 7e), which starts the time delay setting unit 25. The latter is set to the maximum possible duration of time (Fig. 7m), which ensures the complete completion of the transition charge process in the circuit 3.1 under study. During the period of shunting and immediately after shunting of the circuit 3.1 under study, the output of the comparison unit 9 has a logic level signal O (fig.7p), which corresponds to an indication of low insulation resistance relative to a predetermined threshold level determined by the source 17 a reference voltage and a high-resistance resistor 38 of the reference unit 9. During the period of shunting of the circuit under study, the device is simultaneously disconnected from the second and third inputs of the comparator, respectively, the sources 14 and 17 of the measuring and reference voltages from the action of a low-resistance resistor voltage divider in the device. Consequently, during the period of shunting, a predetermined threshold level is determined by a high-resistance resistor 38 and a simulator of the source 17 of the reference voltage — a clock capacitor 15 charged in the period of a de-energized relay 7 (called the shunting period). Disconnection from the second and third inputs of the comparison unit 9 (during the insulation resistance monitoring period) of the sources 14 and 17 of the measuring and reference voltages, respectively, while ensuring control of the insulation resistance due to the voltages present on the charged capacitors 12 and 15, eliminates Causes of interference from the primary AC network by breaking the leakage currents flowing through the high-resistance resistors 37 and 38 of the comparison block 9 and comparable values of the interwinding insulation resistance of the power transformer torus (Fig.8).

If the insulation resistance of the circuit under study is greater than the allowable threshold, then after some time spent on the dosage of the shunt capacitor 4.1 from the timing capacitor 12 (simulating the measuring voltage source 14) via the high-resistance resistor 37 to the comparison unit 9 (fig.7a), The output signal of the logic level 1 (Fig. 7p) appears over the time before the end of the monitoring, which is determined by time delay setting device 25 (Fig. 7f).

This signal is fed to the (K + 1) -th (control) input of the switching unit 5, to the input of the delay unit 20 and to the second input 21 of the key circuit 22 through the first input of the open element AND 18 and the second input of the element OR 19 (Fig. 7c ,at). The front of this signal is read by the counter 44 of the switching unit 5, then the counter information is decrypted so that the output of the decoder 45 shifts the logic level signal O from the first 45.1 to the second 45.2 output, thereby de-energizing the relay 46.1 and activating

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relay 46.2 in the switching unit 5 (Fig. 7 l, m-). Thus, the first circuit under test is disconnected, the output signal of the comparator unit 9 is changed to the logic level O (fig.7p) and the second circuit under investigation is connected, in which the bypass capacitor 4.2 is discharged. The change of the output signal of the comparison unit 9 with the logic level 1 when monitoring the pre-tested circuit with the permissible insulation resistance to the logic level O (fig.7p) when disconnecting this circuit and connecting the next one, in which the shunt capacitor is discharged) contributes to the formation of unit 9 at the output Comparison of pulse signals. Logic level 1, which, passing through the elements of AND 18 and OR 19, are the trigger pulses of the delay unit 20, which zeroes for the key circuit 22 and the counters dp of the counter 44 in the switching block 5 (figr, sv). Thus, an early termination of the control cycle of the first circuit under study and the transition by switching units 5, delay 20, key circuit 22 and time delay adjuster 25 to control of the next circuit occur.

After the key circuit 22 has been zeroed with a pulse signal arriving at the second input 21, the output of RS-trgger 49 is set to a logic level signal O (fig.7d), which ensures the locking of the transistors 50 and 51 and de-energizing the relay 7. Then the connection the output sources of the measuring 14 and reference 17 voltages to the second and third inputs of the comparison unit 9, as well as to the timing capacitors 12 and 15, respectively, for charging them; In the case where the insulation resistance of the circuit under study is less than the allowable value, the signal y An even logical O at the output of the comparison unit 9 is maintained for the entire period determined by the time setting unit 25 (Fig. 7, p, t). At the end of the time period, the output of the setpoint 25 (output Q of the second one-shot 61) receives a pulse signal of the logic level O (fig.7f) indicating that during the time determined by setting 25, the voltage on the circuit under study did not reach

threshold level (fig.7), i.e. the insulation resistance of this circuit, e.g. third, is less than a predetermined acceptable value. When the output pulse is formed by a time setter 25, the RS-flip-flop 26 overturns and at its outputs Q and IQ the level signals are set respectively

(Fig. 7d) and logical 1 At the same time, the signal lamp 32 is turned off. Normally, a 31 smaller lamp lights up (fig. 7c), registering the lowered insulation resistance of the circuit under study. In addition, the signal from the Q output of the RS flip-flop 26 of the logic level O closes the AND 18 element for passing through it and the RSI element 19 of the next pulse signals from the output of the comparison unit 9. The automatic control of the insulation resistance stops. The counter 44 in the switching unit 5 records its state, and the decoder 34 and the signaling unit 35 register the number of the circuit with the rejected insulation resistance.

In order to ensure the continuation of the automatic control of the remaining test circuits by applying a Start signal to the bus 29 (Fig. 76), the RS flip-flop 26 is reset to the initial state. At its outputs Q and Q, the level signals are set respectively to logical 1 (fig. 7d) and logical O. At the same time, the signal signal fflochka 31 is dimmed Less and the shock is illuminated 32% OK. In addition, the signal from the output Q of the RS flip-flop 26 of logic level 1 again provides the resolution to pass through the element And 18 of the next impulse signals from the output of the comparison block 9.

The time setting unit 25 forms at its output (output Q of the one-vibrator 61) a delayed pulse signal only if during the formation of the delay by a single vibrator 58, the input signal does not change from its initial state to low to high level. If during the formation of the delay by the one-shot 58, at its input a signal changes to the initial state, then the one-shot 61 is closed at the R input with an inverted low level signal.

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Consequently, when the output of the unit 9 of the comparison of the signal of the logic level 1 (corresponding to the characteristic of the insulation resistance of the circuit under study exceeds a predetermined limit), until the end of the set time of the setting device 25, the output of the logic level O will not be generated (FIG. 7a), therefore, the RS flip-flop 26 will still be in the initial state, in which at its Q-output the signal of the logic level 1 is maintained, ensuring the passage of the signals of the logic level 1 from the output of block 9 cf through the elements 18 and 19 tim next investigated in the control circuits (fig.7r, s, c).

Simultaneously with the switching of the studied circuits, their numbers are recorded in the form of numbers on the display unit 35, operating from the decoder 34, connected to the information outputs of the counter 44 in the switching unit 5.

Breaking the leakage circuit through the inter-winding insulation resistance completely eliminates the causes of pickups in the primary network at the inputs, and hence at the output of the comparator unit, as a result of which the interference immunity of the device increases.

An insulation resistance monitoring device containing measuring and reference voltage sources, To terminals for connecting To the studied circuits, shunted by capacitors, series-connected switching unit, comparison unit and AND element, series-connected OR element, delay unit, time delay master , as well as turnips, K terminals for connecting the control object are connected to the corresponding K inputs of the switching unit, the first output of which is connected through serially connected first The normally closed contact group of the relay and the first low-resistance resistor are connected to the common bus, and through the second normally closed contact group of the relay and the second low-resistance resistor in series with the second input of the comparator unit, the second input of the elements OR is connected to the start bus, the output of the OR element is connected to the second input of the key circuit and to the (K + 1) th (control) input of the switching unit, the second output of the key circuit is connected to the first output of the relay winding, the second exit of which is connected to the common bus, zeroing connected to the third input of the key circuit and the (K + 2) th input of the switching unit, characterized in that in order to improve the noise immunity, a decoder, an indication unit, two timing capacitors, two signal indicators, a HE element, an RS trigger and a third are entered into it. and the fourth normally closed contact groups of the relay, the positive pole of the measuring voltage source through the third normal al closed contact group of the relay is connected to the second input of the comparator unit, and the first lining of the first clock capacitor, the positive pole of the source of the reference voltage through even

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the twisted normally closed contact group of the relay is connected to the third input of the comparator unit and the first plate of the second clock capacitor, the second plates of the first and second clock capacitors and the negative poles of the measuring and reference voltage sources are connected to the common bus, the trigger bus is NOT connected to the R input RS flip-flop, the S-input of which is connected to the output of the master clock, the inverse Q-output is connected to the second input of the And element and to the first pin of the first signal indicator, and the direct Q-out d - a first terminal of a second indicator signal, the second terminals of the signal indicator connected to a positive power supply bus, M inputs information decoder connected to respective outputs of the switching unit M, N decoder outputs are connected to N inputs of the alarm unit.

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Claims (1)

Claim An insulation resistance control device containing measuring and reference voltage sources, K terminals for connecting To the studied circuits shunted by capacitors, series-connected switching unit, comparison unit and AND element, series-connected OR element, delay unit, key circuit and time delay adjuster, and also a relay, K terminals for connecting the monitoring object are connected to the corresponding K inputs of the switching unit, the first output of which is connected in series through the first The normally closed contact group of the relay and the first low-resistance resistor are connected to the common bus, and through the second normally closed contact group of the relay and the second low-resistance resistor - with the second input of the comparison unit in series, the second input of the OR element is connected to the start bus, the output of the OR element is connected with the second input of the key circuit and with the (K + 1) -m (control) input of the switching unit, the second output of the key circuit is connected to the first output of the relay winding, the second output of which is connected to the common bus, the zeroing bus is connected on with the third input of the key circuit and the (K + 2) -th input of the switching unit, characterized in that, in order to increase the noise immunity, a decoder, an indication unit, two timing capacitors, and two signal indicators, an element NOT, RS- are introduced into it trigger and the third and fourth normally closed contact groups of the relay, the positive pole of the measuring voltage source through the 20 third normally closed contact group of the relay is connected to the second input of the comparison unit, and the first lining of the first timing capacitor, the positive The fourth pole of the reference voltage source is connected through the fourth normally closed contact group of the relay to the third input of the comparison unit and the first plate of the second timing capacitor, the second plates of the first and second timing capacitors and the negative poles of the measuring and reference voltage sources are connected to a common bus, bus start through the element is NOT connected to the R-input of the RS-flip-flop, the S-input of which is connected to the output of the delay timer, the inverse Q-output with the second input of the element And and with the first output House first signal indicator, and a straight line Q-output - to a first terminal of the second signaling indicator, the second terminals of signal lights are connected with a positive power bus, M data inputs of the decoder are connected to respective M outputs of the switching unit, N decoder outputs are connected to the N inputs of the alarm unit. Figure 2 I Mouth Fig 5 Figb He took in __] _______ ^ PutSK D a. 28 | 5. 29 | g In, out. ιέ 26 i <ν _2ί . . (94ff ‘t_. ML ^: J. 22 - (bf / x / yr ^ r ⁵ (Exit 64 $ - ^U '(Exit T ^ --— * ⁷ i | - L (46.1) 1 --- * (46 ⁵ 2) l --- ^H '(46jA— (46 ^S 4) ^ --- 9k Bx.1 P. 9 i P. output f with "| _ '· i x. "L__ 4 3f t .. N ° P ^{ma on} j? / W ' l ’ - ^ Σ. —--- ^ Restart I p t N2 KBM Whitefish Norma 4 goals t i t i --_ _t - ~ t 1'On circuit N4 U supports ”, at the input” - ”composer ^ Sv ί ⁴ - I ---- t _h— C = U ₍ limp.Ny.nia control I.Murlsovnett.kL ^{n on} Vkh h ^ Impils vst.tk>, ULA *. . } input P ____ „_____________ ^ £ Norm Less ”on. light bulb 31 FIG. 7 Fi g. 8