SU1594550A1 - Subscribers interface - Google Patents

Abstract

The invention relates to computing, in particular, to devices for interfacing between subscribers in a ring structure system, and can be used for receiving and transmitting information in systems using bit-oriented synchronous communication protocols for exchange. The purpose of the invention is to expand the functionality by providing two-way data exchange between any subscribers of the ring system. The device contains a receiver, a transmitter, a synchronization unit, a register block, a decoder block, a memory block, two counters, a bit-stuffing remover block, a receive control block, four AND elements, three OR elements, eight triggers, a command register, a transfer register, a register control characters, transmission control unit, bit stuffing addition unit, one-shot. 1 hp ff, 16 ill.

Description

The invention relates to computing, in particular, to user interface devices in a ring structure system, and can be used to receive and transmit information in systems using bit-oriented

synchronous communication protocols

The purpose of the invention is to expand the functional capabilities of the device by providing two-way communication between any subscribers of the ring system.

Fig, 1 shows the block diagram of the device; figure 2 - diagram of the synchronization unit; Fig. 3 is a block diagram of registers; figure 4 - block diagram

decoders; Fig. 5 is a block diagram of a memory block; Fig. 6 is a diagram of a bit stuffing remover; 7 is a block diagram of the reception control; Fig. 8 is a block flow bit stuffing block diagram; figure 9 - the structure of the information frame; FIGS. 10-15 are timing diagrams for the operation of the device and its units: FIG. 16 is an electrical diagram of one-bit comm.

ACCESSORIES) FOR WHAT AREA WAITING

subscriber subscriber contains Poiemnik 1, transmitter 2, synchronization block 3, register block 4, decoder block 5, memory block 6, first counter 7, block stuff removing unit 8, reception control block 9, first element

with

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ment And 10, first element OR 11, first 12, second 13 and third 14 flip-flops, second counter 15, command register 16, transfer register 17, control character register 18, transfer control unit 19, bit stuffing addition unit 20, second 21 and third 22 elements OR, second 23, third 24 and fourth 25 elements And, fourth 26, fifth 27, sixth 28, seventh 29 and eighth 30 triggers and one-shot 31.

The synchronization unit 3 is designed to provide bit synchronization of the received, retransmitted and transmitted information and to generate a series of non-overlapping phase pulses, ensuring synchronization of the operation of all units of the device. It contains the master oscillator 32, the frequency divider 33, the decoder 34, the filter 35, the pulse shaper 36, the element 37, the first 28, the second 39 and the third 40 flip-flops, the element 41 and the adder 42 modulo two.

The second 39 and third 40 triggers, the HE 41 element and the modulator 42 modulo two are designed to allocate the significant moment of the input signal from the information sequence to the input of the synchronization unit-3. These significant moments affect the divider 33 of parts, synchronizing the phase of the local generator with the phase received by the information. A series of non-overlapping phase pulses from the output of the decoder 34 is supplied to the second input of synchronization unit 3 and dp is used to synchronize the operation of the device unit, and the clock frequency passing through the filter 35 and shaper 36 pulses to the first output of synchronization unit 3 is used by dp of transmitter 2 and operation control block 6 of memory and block 20 add bit-stuffing.

The register unit 4 is designed for spatial-temporal separation of the input information stream for the purpose of ensuring the operation of the decoder unit 5 and performs serial-parallel conversion of the received data when recording them in the memory unit 6. It contains the first 43, second 44, third 45 and quarter 46 shift registers with parallel outputs.

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Block 5 of the decoders is designed dp decryption of service and management information, framing information ,; ration frame. It contains the decoder 47 units of the third register, the decoder 48 of the flag of the third register, de-: the encoder 49 address of the subscriber, the decoder 50 units.-Fourth register, the decoder 51 of the flag of the first register, the decoder 52 of the frame end, the decoder 53 marker, the first 54, second 55, third 56 and fourth 57 elements But

One of the pulses of a non-overlapping series of phases arrives through the first input of block 5 of the decoder, gating the first 54, second 55 and fourth 57 elements I. At the output of element 56, an impulse appears when the subscriber's address is decoded and enters the second input of block 5 decoder. At its third output, an impulse appears when the declining flag is decrypted. At the fourth and first block exits

A 5 pulse appears at the time of decoding the end of the frame. The fifth output pulse occurs when the control pattern of the marker is decrypted.

The memory unit 6 is intended for buffering the information frame received from the network and transmitted to the network. It contains a block of 58 static memory chips (storage) of the type K565 RU2, a decoder 59, a reversible counter of the memory address 60, the first 61, the second 62, the third 63 and. Fourth 64 elements 2I-2ISH and element NO.

The elements 2I-2ShSh 61 64 collectively represent a switch of data and control signals at the inputs of the accumulator 58 and the counter 60 of the address. The address inputs of all memory chips are interconnected one by one and connected, to the output of the address counter 60 and the input of the decoder 59. The information outputs of the storage chip 58 are fed to the first output of the memory block 6, and the second output is connected to the output of the decoder 59. Element NOT 65 is used to control the switch.

The data in memory block 6 is received from two directions depending on the control signal at the ninth input of memory block 6. To the second input block

The data received from the network is received in the 6th and the data on the eighth input - 30

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from the subscriber, intended for transmission to the network. The output of the second element 2I-2ILI 62 is connected to the subtracting I stroke of the address counter 60, and its summing input is connected to the output of the fourth element 2I-2ILI 64. The output signal from the third element 2I-2ISH1 63 is fed to the reset input of the counter 60 of the address

Bit-stuffing removal unit 8 is designed to remove zeros from the received information, which are added to the information part when transmitting dp of separating the control characters from the information part of the packet transmitted through the ring. It contains a counter 66, a decoder 67, a trigger 68, a first 69, a second 70, a third 71, a quarter 72 and a fifth of 73 elements AND, an element NOT 74, the first 75 and a second 76 elements OR.

Information transmitted over the ring., Tsu, through the first input of block 8 goes to the elements And 69 and 72, and also through the element NOT 74 - to the input of the element And 70. Through the second input to the first 69, second 70 and Fifth 73 elements And one of the clock series of the synchronization unit 3 arrives. The third input is a control one and is intended for allowing the operation of block 8. The zero signal level through the OR 75 element prohibits the switching of counter 66 and blocks And 71 and 72 elements.

The bit-stuffing removal unit 8 operates as follows. After the enabling potential arrives at the third input of the unit 8 of the counter 66, it switches to the next state only after the arrival of several units. If the received information is less than five units of a row, zero appears, it resets the counter 66 to its original state. If the counter 66 pushes another five units, there is a potential at the output of the decoder 67 that sets the trigger 68 to the zero state. Then, if the first input of the block 8 has the next zero bit of information, the And 72 element will be blocked, will lead to blocking the output of the output pulse of block 8, which is the gate of the block 4 receiving registers.

The reception control unit 9 is designed to calculate the check sequence.

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the accuracy of the frame information and verify the reception of incoming information. It contains the first 77 and second 78 registers, the first 79, the second 80 and the third 81 modulo two, the first 82, the second 83, the third 84, the fourth 85, the fifth 86 and the sixth 87 elements I.

Registers 77 and 78 and modulo-modulators 79-81 combine to represent the counting pattern of a control code sequence using constituent polynomial 1. Elements AND 830

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87 is a zero decoder.

The essence of the operation of block 9 is reduced to ... counting the checksum on the generator polynomial and adding it to the control one. If there is no distortion of information in the communication channel, then the result of the check is the zero state of the registers of block 9 and its output testifying to the correct reception of information.

Command register 16 is designed to control the operating modes of the device and is three triggers with the possibility of their installation and reset by the subscriber. The first output sets the direction of recording information in the memory block 6 from the side of the communication line or from the subscriber. The second output is an output of device operation readiness as part of a ring data transmission system. The third output determines the mode of reception or transmission of information.

The transmission control unit 19 is intended to allow a frame to form a control sequence using a generator; X + X + + X + 1 polynomial. This two-byte control sequence is formed at the end of the information part of the message and serves to .... check the correctness of the transmission at the receiving points of the ring system. The transmission control unit 19 is constructed similarly to the reception control unit 9 shown in FIG. 7, and differs from it in the absence of a zero decoding scheme, i.e., elements 83-87. The output of the block 19 in this case is the output of the older shift offset. register 78, from which the control sequence under control

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These pulses from the first output of the synchronization unit 3 are fed to the second input of the third element, there is no shift pulse of the transmitting registers, as a result of which the information transmitted to the communication line is. zero bit is added. If in the transmitted information there is a further

the first synchronous input 109 of block 4 of registers for shifting information without deleting bit stuffing,

the second software synchronization of block 4 for information shift with the removal of bit-stepping,

serial information output unit 4 for registration

.--. , -, fj. --r i -I - - .. -d vi A jTi 1 oaipm

less than five units, the closest zero, Q information to the adjacent device col- bit every groove of the system

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The j bits each time resets the counter I 88 to the zero state and it starts i counting again the next few i units o. Thus,

; transparency is transmitted, information ..} 5: The block of adding bit-stuffing co-J holds the counter 88, the decoder 89, the trigger 90, the second element AND-NOT 911,:: the first 92 and the second 93 elements And,: the HE element 94. first element: AND-NOT 95o

; The links presented on fkg.1:; information input 96 device-: va, connected to two-wire; input line

information output 97 of the device connected to a two-wire output communication line,

: a group of data buses 98 from a subscriber, through which information is transmitted in a parallel code,

bus 99 controls from the subscriber, through which the strobe signals are transmitted, accompanying information on the buses 98 data from the subscriber,

output 100, a status indicator indicating that a received message is to be transmitted to the subscriber, is set when an information frame is received on the local network, is reset after the information frame is transmitted to the subscriber,

a group of data buses 101 from the device on which information is transmitted in parallel code to the subscriber,

information output 102 of the receiver. one ,

clock input 103 of transmitter 2, information serial vhrd 104 of transmitter 2, input 105 of the mode setting of synchronization unit 3,

a clock input 106 of a synchronization unit 3 for synchronizing data transmission to a local network,

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local network

parallel information outputs 112-114 of block 4 for organizing the decoding of the control characters of the frame in block 5 of decoders,

serial information output 115 of block 4 for organizing the operation of block 9 of the reception control,

the first permitting input 116 of the block 5 of the decoders, through which the gating of the AND 54-57 elements (FIG. 4) is performed when decrypting the control characters,

parallel information inputs. 117-119 dyons of block 5 decoders, through which received code combinations separated in time,

the second enabling input 120, which receives the potential from the second output of the register of 16 commands, allowing the device to decrypt the address coming from the data transmission network,

the output 121 of the sign of the decoding of the end of the frame in the received message, the code 122 of the sign of the decryption of the device address, which occurs when the device is accessed by other network subscribers at the moment. Identifying (decrypting) this device its own address,

output 123 of the flag decryption flag, which is opened in the received message,

the output 124 is a sign of decryption of the flag, which closes in the received message; ,

output 125 of the marker decoding feature,

a clock input 126 of memory block 6, through which gating is carried out to the block received

clock output 107 of block 3 of the synchronous data transmission network.

to synchronize data reception from the line,

serial information input 108 blocks 4 registers.

parallel input 127 of block 6 pa- .: mi, to which it is received from the data data transmission network, converted by block 4 registers

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the first synchronous input 109 of block 4 of registers for shifting information without deleting bit stuffing,

the second software synchronization of block 4 for information shift with the removal of bit-stepping,

serial information output unit 4 for registration

 -I - - .. -g vi A jTi 1 oaipm

Q information to the adjacent kolleppl gt tlatt device, ““ “

, Q information to the adjacent kolleppl gt tlatt device, „“ “

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local network

parallel information outputs 112-114 of block 4 for organizing the decoding of the control characters of the frame in block 5 of decoders,

serial information output 115 of block 4 for organizing the operation of block 9 of the reception control,

the first permitting input 116 of the block 5 of the decoders, through which the gating of the AND 54-57 elements (FIG. 4) is performed when decrypting the control characters,

parallel information inputs. 117-119 dyons of block 5 decoders, through which received code combinations separated in time,

the second enabling input 120, which receives the potential from the second output of the register of 16 commands, allowing the device to decrypt the address coming from the data transmission network,

the output 121 of the sign of the decoding of the end of the frame in the received message, the code 122 of the sign of the decryption of the device address, which occurs when the device is accessed by other network subscribers at the moment. Identifying (decrypting) this device its own address,

output 123 of the flag decryption flag, which is opened in the received message,

the output 124 is a sign of decryption of the flag, which closes in the received message; ,

output 125 of the marker decoding feature,

a clock input 126 of memory block 6, through which gating is carried out to the block received

, data transmission network information.

 data transmission network information.

parallel input 127 of block 6 pa- .: mi, to which it is received from the data data transmission network, converted by block 4 registre

ditch from sequential code to parallel

an input 128 for resetting the memory address counter 60 (FIG. 5) when receiving information in memory block 6 from the data transmission network side,

the input 129 of the strobe of writing the next data byte to the memory block 6 when receiving information from the communication line,

The reset memory reset 130 of the memory address counter 60 when the information is written to the memory block 6 on the subscriber’s side, the input synchronization input 131 of the information is sent to the memory block 6 for transmitting it from the subscriber to the communication line,

the input 132 of the system of reading information from memory block 6 when it is output to the communication line,

a group of parallel buses 133, data from a subscriber for recording information in block 6 of memory for transmitting to a communication line,

input 134 controls the direction of writing and reading data in memory block 6, intended for switching data write-read directions on elements 2I-2ILI 61-64 (FIG. 5), a group of parallel buses 135, data to a subscriber for the subscriber to read the received information from the communication line

the output 136 of the decryption attribute of the zero state of the counter 60 of the memory address, indicating that the subscriber has read the last data byte from the received information frame,

the input 137 of the resolution of the operation of the counter 7,

the clock input 138 of the counter 7, century. The output 139 of the counter 7, intended to form the output impulse after eight pulses at its clock input,

information input 140 block 8 removal bit stuffing,

a clock input 141 of a bit-removing unit 8,

input 142 permitting the operation of the bit-removing unit 8,

information output 143 of bit-staffing removal unit 8,

the clock input 144 of the reception control unit 9,

strobe blocking input 145, designed to block the strobe in reception control unit 9 at the moment of bit stuffing removal.

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serial information input 146 of the reception control unit 9,

an input 147 of resetting the registers 77 and 78 of the control and reception unit 9 (Fig. 7) to the zero state,

the output 148 of block 9, intended to indicate the correctness of the reception of the information frame,

input 149 of the element, And 10, designed to analyze the correctness of the information frame received from the communication line,

the input 150 of the element 10, on which there is a potential that determines the mode of reception of the information frame from the communication line,

the input 151 of the element 10, which receives a pulse at the time block 5 decoders detect the sign of the end of the received frame,

the output 152 of the AND 10 element, designed to determine the moment of converting the control symbol. The end of the frame into the Frame is received by replacing the last zero in the control symbol by one when conditions at the inputs L 49-151 are fulfilled,

an input 153 of an OR 11 element for retransmitting through it a serial code received and simultaneously transmitted to the communication line,

input 154 of the element OR 11 to convert the character End of the frame to the Frame is received at the time determined by the set of conditions by the element

And 10,

output 155 of the element OR 11, through which the relayed information passes,

input 156 reset trigger 12 to the zero state,

the input 157 of the installation of the trigger 12 in one state,

the output 158 of the trigger 12 intended to enable the operation of the memory block 6 and the reception control block 9 and to set the resolution potential - at input 150 of the AND 10 element,

the trigger setting input 159 13 in one state,

input 160 reset trigger 13 to well--., left state,

the output 161 of the trigger 12, intended to enable the operation of the counter 7 and the bit-stuffing removal unit 8, and to enable the installation of the trigger 12 in a single state as well;

to reset it to the zero state,

input 162 reset the trigger 14 to the zero state,

the input 163 of setting the trigger 14 into one state,, the output 164 of the trigger 14 for transmitting a signal Attention to the subscriber, intended to inform the subscriber that a message from the ring network has been received in memory block 6,

the input 165 of the resolution of the operation of the counter 15,

counting input 166 counter 15,

the output 167 of the counter 15, on which a signal appears after counting by eight clock signals on the counting clock, m. after sending one byte of information from the memory block 6 to the communication line,

a group of information inputs 168 command register for writing the command code to the register 16,

control (strobe) input 169 of the register of 16 commands,

the first output 170 of the register 16 of commands for setting the direction of data transfer in memory block 6 (if the bit is equal to zero, it sets the data recording mode on the communication line side, and if the unit is equal, the data writing mode is set in block 6 on the subscriber side)

the second output 171 of the command register 16 intended to enable operation of the device as part of a data network (the state of logical zero prohibits operation as part of the network, and the state of the logical unit allows such operation),

the third output 172 of the register of 16 commands is a sign of the end of the recording of the information array in the memory block 6 on the subscriber’s side; setting this bit to the state of the logical unit; the subscriber switches the device into the search mode of the control combination. finding such a combination.

clock input 173 register 17

reductions to which shifting clock pulses arrive,

input 174 permit the operation of the register 17 of the transfer.

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clock input 175 parallel writing data byte to transfer register 17 (strobe input),

group of parallel information inputs 176 register 17,

serial information output 177 of the transmission register 17,

clock input 178 parallel registering in the register 18 codes of control characters, the flag ending and the end of the frame, typed by jumpers in the form of combinations of logical levels of zeros and ones at its inputs (not shown), since they have no functional connection with the rest of the circuit,

a clock input 179 of register 18 for supplying shift pulses,

input 180 of the resolution of the shift information in the register 18,

serial information output 181 of register 18,

the gate lock input 182 in the transmission control block 19 at the time of adding bit stuffing,

serial information input 183 block 19,

clock input 184 block 19, input 185 reset registers, pred. assigned to enable operation of block 19,

serial information output 186 of the transmission control unit 19,

the input 187 of the resolution of the operation of the block 20 add bit-stuffing,

a clock input 188 of a bit-adding unit 20,

serial information input 189 block 20,

the output 190 of block 20, the input: 191 of the element OR 21, designed to transmit the relayed information,

an input L 92 of the element OR 21 intended to transmit information from a given subscriber to a ring system,

the input 193 of the OR element 21, for converting the control combination of the Marker into the combination Flag opening, the output 194 of the element OR 21, the input 195 of the element OR 22, intended for the transfer of matching symbols,

an input 196 of the element OR 22 for transmitting the control. one

Noah sequence of the frame formed by the block 19 control transmission

an input 197 of the element OR 22 for transmitting the information part of the frame,

output 198 of the element OR 22,

serial information input 199 of the element 23 for transmitting information in the retransmission mode,

the input 200 of the blocking element And 23, designed to prohibit retransmissions during the transmission of information from this subscriber to the ring system,

the output 201 of the element And 23,

the input 202 of the element 24 and intended to add bit-stuffing to the transmitted information

an input 243 of an AND 24 element intended to transmit a frame formed for transmission to the ring system,

output 204 element And 24,

the input element 205 of AND 25, intended to allow the device to react to the control combination Marker after the subscriber has recorded the information to be transmitted to the buffer memory of block 6,

the input 206 of the element AND 25, which receives the sign of decoding the control combination Marker,

output 207 of the element And 25,

the reset input 208 of the trigger 26 to the initial state,

trigger setup input 209 26,

the output 210 of the trigger 26, intended to enable the operation of the register 18 of control characters of the block 20 of adding bit-stuffing and the counter 15 of installation to the unit of trigger 27 and prohibiting the passage of information through the element 23 in the transmission mode- (transmission trigger),

input 211 installation unit trigger 27,

input 212 reset to zero trigger

27.

the output 213 of the flip-flop 27, intended to permit the operation of the transmission register 17 and the one-shot 31, and to enable the switching of the flip-flops. 28 and 30 (trigger permits information),

trigger input 214 reset trigger 28, trigger setup input 215 28, trigger trigger output 216 28, intended

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Chlenny to enable the operation of the control unit 19 and reset the trigger 29,

flush trigger reset input 217 29, flip-flop setup input 218, flip-flop output 219 29 are used to enable information shift in the control character register 18 and reset to the initial state 10 of flip-flop 26,

input 220 data of the counting trigger 30,

counting input 221 trigger 30,

output 222 of trigger 30, predneena J5 to control the switching of the triggers 28 and 29,

the input 223 of starting and permitting the operation of the one-shot 31 during the retrieval of information from the buffer memory of block 6 to the communication line,

input 224 launch of one-shot 31 "

the output 225 of the one-shot 31, intended to carry out the reading information pulses from the block 6 of the memory 25 and write this information to the transfer register 17.

In the mode of receiving information from the communication line (FIG. 10), before the device starts operating, the output 171.The register 30 16 commands must be set by the subscriber to the state of a logical unit (FIG. Yu) in order to enable the device to operate as part of a ring network. . data transmission This signal through the input 120 of the block 5 decoders enters the element And 56 of the block 5 and permits the device to react when it recognizes its own address. The output 170 of the register of 16 commands must be set to the logical state. whose zero () is to set the appropriate direction for writing and reading information in memory block 6 (Fig. 5).

de Being in receive mode, the device retransmits the received information. The information at the output 97 of the device corresponds exactly to the information at its input 96 with a delay due to the retransmission by one bit. Fig. L O shows the information at the output 102 of the receiver 1 ((} mg.10v) and at the input 104 of the transmission 2 (fig.10m).

When a control symbol is added, the Opening Flag (Fig. XI) of the decoder block 5 identifies it and issues a pulse at its output 123 (Fig. South) setting

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Flag starts block 8

the output 161 of the trigger 13 (FIG. YD) to the state of the logical unit. This g is being prepared for installation in the state of the logical unit of the output 157 of the trigger 12, which will occur if the kggr transmitted at this moment through the ring network of this subscriber., In such a case, after decrypting the Flag of the decoder block 5 that opens at the output 122, a pulse is received (fig. Ue), indicating that the address of this device is recognized by the fe block 5. This pulse is set; Puts the output 158 of the trigger 12 I (FIG.) into the logical state; units.

; From the moment of recognition 1i: otkryshayuschego

: remove bit-stuffing, at the output of which 143 I are formed; clock pulses i (fig.Huz) controlling the operation; block 4 registers; block 9 controls: reception and counter 7. Having read the last I eight eight shear pulses: at its input, it outputs at its output; de 139 impulse (Fig. Ju), indicating that in block 46 of block 4 of registers (fig 3); accumulated byte of information for writing to memory block 6. The data from the output 114 of the block 4 of registers is received in the remote code at the input 127 of the memory block and gated by this pulse on the input 129 of block 6. The same pulse in memory block 6 performs: switching the next address of the memory cell.

If the device address is recognized (Fig. 1Oe), the serial-parallel conversion of the incoming information and its writing to the payt of block 6 continues. Since the information shift,

registers produced clock

pulses from output 143 of the bit-stuffing removal unit 8, informal is recorded in memory unit 6; , days freed from bit stuffing. The same information is relayed from output 11I of block 4 of registers under the action of clock pulses on its synchronous input U9, received directly from output 107 of block 3 of synchronization, therefore it is not freed from bit stuffing, but transmitted in unchanged form (Fig. 10m). After decrypting the control character, the flag that krehsayushchy (fig.uv)

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trigger 13 is reset (fig.Yud)

and trigger I 2 (Fig. 10g). Wherein

the recording of information in the memory block 6 is stopped.

At the moment of passing the last control character in this message. The end of the frame at the output 121 of the decoder block 5 is a corresponding impulse (Fig. 10), which gates the potential coming from the output 148 of the receive control block 9 (FIG. 10L). Zero potential level. la indicates the coincidence of control sequences, i.e. normal termination of receiving information from the communication line. The pulse from output 121 of block 5, having passed through the OR element 11, replaces the last zero in the control symbol End of Frame by one, thereby transforming it into.

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Frame symbol is received (Fig. 10m). Od5

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A pulse from the output 152 of the first element AND 10 sets the output 164 of the flip-flop 14 to one state, informing the subscriber of the received message in the memory block 6. This completes the procedure for receiving a frame of information from the ring network.

In the information transfer mode to the ring network (Fig. 11), before starting operation in this mode, the output 17 of the register 16 of commands (Fig. D1 a) and the output 170 of the register 16 (Fig. 11 b) must be set to the state of a logical unit for ensuring the operation of the device in the ring network in the mode of data transmission from the subscriber. The subscriber then writes the information to be transmitted to the block 6 of the buffer memory and sets the output 172 of the register 16 of commands to the state of logical one.

(fig.Pv).

After that, the decoder unit 5 analyzes the circulating information for the presence of a control marker combination (Fig. 11 g). Upon detection of such a combination, an impulse (Fig. ID) appears at the output 125 of block 5, setting the output 210 of the trigger 26 to the state of a logical unit (Fig. Lie). This is allowed

the operation of block 20 for adding bit-staf-t of the fing (Fig.L) and register 18 of control characters, forming control characters in the transmitted and input 103 of transmitter 2 (Fig.Pv) of the sequence, and output 213 of the trigger 27 is also set to one ( 11 and). At the time of installation of the trigger 27, the potential from its output 210 enters the input 200 of the element I 23 and prohibits its passage through it. information on the input 191 of the second element OR 21. Pulse output 125. block 5 of the decoder also passes through the element AND 25 on the element 19 OR 193. This leads to the replacement of the last unit of the marker with a zero in the control combination, which is equivalent to replacing the control symbol Marker with the Open flag (Fig. From).

The signal from the output 213 of the trigger 27 (Fig. Pi) triggers the vibrator 31 to the input 223. As a result, the output 225 of the one-oscillator 31 produces a pulse (Fig. PC). This pulse is used to read information from memory block 6, then switch the address counter 60 therein and write the read byte to transfer register 17. After that, the clock-pulses received from the block 20 to-L of bit-stuffing (FIG. PF) shift the information in the transfer register 17 by performing parallel-serial conversion. The shift is performed so that, if necessary, bit-stuffing is added to the transmitted information.

After counting the transmitted bits of the bits transmitted by the counter 15, an impulse appears on its input code 167 (Fig. Pl), which enters the input 22D of the one-shot 31. As a result, the next impulse produces the next impulse (fig.Pc), according to which it is produced. reads the next byte of information from memory block 6 and writes it to transfer register 17. Then, by supplying the shift pulses to the input of the L 73 register 17, serial conversion is carried out in parallel and transmitted to the communication line via the input 104 of the transmitter 2 (Fig. From) the next data byte.

The described processes are repeated until the complete transfer of the entire array from the buffer memory of block 6 to the in-line St. -. zi Upon completion of the transfer of the entire array, the content 1a of my memory address counter 60 is reduced to zero, which is fixed by the decoder 59 of block 6.

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As a result, the output 136 of block 6 establishes a zero potential (Fig. I1m), by which the output 213 of the trigger 27 is switched to the zero state (Fig.11 and 11), the operation of the transmission register 17 and the pulse former is disabled and the trigger 30 is switched and 28 (fig.11n, o).

Next, under the action of the shear pulses fed to the input 183 of the transmission control unit, the frame check sequence is output (FIG. Pz). After transmitting the first eight bits of the check sequence, the counter 15 at the output 167 generates a signal (FIG. PL), which switches the counting trigger 30 (FIG. PN). Next, the transmission control unit sends the second byte of the control sequence to the transmitter 2, after which the pulse from the output of the second counter 15 (Fig. PL) re-switches trigger 30. 30. Trigger 28 (11 o) is reset on the front of this switch, prohibiting operation of block 19 controls and sets the seventh trigger 29 (fGoPP), allowing the shift of information in the register 18 control characters. Under the action of shifting pulses occurs -. their serial transfer to the communication line. After every eight bits, the counter 15 triggers 30 (switches 11l, n). After issuing the End of Frame symbol (Fig. 11c), trigger 30 is re-switched (Fig. Mon), which leads to trigger 29 switch (Fig.Pn), which prohibits the operation of the control character register 18 and causes reset of the trigger 26 (Fig. .lie) in the initial state. This completes the procedure for transferring the frame to the ring network.

The timing diagram of the operation of the memory block 6 during the transmission of information to the communication line is shown in Fig. 12. The timing diagram of the operation of the memory block 6 upon receiving information from the communication line is shown in FIG.

In the mode of information transfer to LI: -. A communication cue at the input 134 of the memory block 6 (Fig. 5) must be set by the subscriber to the level of the logical unit (Fig. 12a) -dn setting the corresponding transmission direction in the memory block 6. And this level must be maintained for the entire duration of the transmission. Before starting operation, a reset pulse is applied to one of the inputs 130 by the subscriber; the counter sets the 60 memory addresses to its initial state (Fig. 12b). The outputs of the counter 60 at 30A are reset to the plate (Fig. 12b). After that, the memory block I is ready to receive information from the user.

.I Data from the subscriber arrives at INPUTS 133 of block b and is accompanied by an I gate at the input 130 (Fig. 12d, g). | By strobe, the byte is written; the data in drive 58 of block b and switching | of counter 60 of the address. Then: the subscriber sets to the inputs 133; the next data byte and accompanies; his strobe to the input 130 (fig.12g, d). This procedure is repeated further and continues until the subscriber enters all the necessary information in block 6: DG1H transfer data array. After: this, the subscriber commands the device to transmit the recorded array to the ring system by setting the state of command register 16 (FIG. Pv) to the state of the logical unit of output 172. Having received the command. The device performs the transmission mode as shown in FIG. Moreover, the output pulses of the generator 36 (Fig. Ik) are supplied to the input 132 of the memory block 6 (Fig. 12e) and are reading gates of information from block 6. The gates carry information from block 135 of block 6 ( Fig. 1 For) and write it to the transfer register 17. By

turning on the counter 60 of the memory address in the opposite direction after each byte read and transmitted to the communication line (Fig. 12b). Upon completion of the transfer of the entire array, the outputs of the counter 60 are set to the zero state (Fig. 12b), which is determined by the decoder 59, which at its output 136 generates a signal (Fig. 12i) resetting the trigger 27 to the zero state and thereby inhibits operation shaper 36. This completes the cycle of transmitting the frame of information through the block b to the communication line.

ten

15

At the input 134 of the block 6 set-; The level is a logical zero, which must be maintained for the entire duration of the device operation in the receive mode (FIG. 1, Over). The counter 60 before starting the operation must be set to the zero state, if it is not in it, with a signal at the input 130 of block 6 (Fig. 136). After resetting the counter 60 to zero (Fig. 13b), the block b is ready to receive information from the communication line.

When the information byte is received from the communication line i. In accordance with the diagram in Fig. 10, the data is set at the inputs 127 of the block b (Fig. 1Gr) and is accompanied by a recording gate at the input 129 of the block 6 (Fig. A). This gate records information into the drive 58 and switches the memory address counter 60. Recording information and switching the counter in the forward direction occurs until the entire information frame is received from the communication line. As evidenced by the signal at the output 164 of the trigger 14 (Fig.Un), which goes to the subscriber.

The subscriber, having received a signal about the presence of communicating communication for him in block 6, by applying read strobe signals to input 130 of block b (Fig. 13e) j reads 6 bytes of data received in the block, which are sent to block 135 6 (Fig.13zh). : The read pulses switch the counter 60 of the address in the opposite direction after each successive one to the same pulses before the read byte. It happens

20

25

thirty

35

until the counter 60 is exhausted to zero (Fig.Pv), i.e. until the entire data array from block 6 has been read. The zero state of the counter

45 is determined by the decoder 59 of block 6, which causes the zero signal to exit 136 of block 6 (Fig. 13z). This signal causes reset of trigger 14, which notifies the subscriber of completion

5Q cycle receiving data from the ring cei -.- ty. At this, the operation of the block b on receiving from the network and transmitting to the subscriber the current information frame ends. Time diagram of the block

55 8 bit-stuffing removal is shown in FIG. 14, and block 8 itself is shown in

In the information reception mode of the communication line, the memory unit 6 operates as follows.

The subscriber, having received a signal about the presence of communicating communication for him in block 6, by applying read strobe signals to input 130 of block b (Fig. 13e) j reads 6 bytes of data received in the block, which are sent to block 135 6 (Fig.13zh). : Read pulses switch the address counter 60 in the opposite direction after each byte before the next read. It happens

until the counter 60 is exhausted to zero (Fig.Pv), i.e. until the entire data array from block 6 has been read. The zero state of the counter

45 is determined by the decoder 59 of block 6, which causes the zero signal to exit 136 of block 6 (Fig. 13z). This signal causes reset of trigger 14, which notifies the subscriber of completion

Q cycle receiving data from the ring cei -.- ty. At this, the operation of the block b on receiving from the network and transmitting to the subscriber the current information frame ends. Time diagram of the block

5 8 bit-stuffing removal is shown in FIG. 14, and block 8 itself is shown in

| FIG. b.

The unit for removing bit stuffing works as follows. In the original

the state at input 142 of block 8 receives a zero potential (figa), blocking elements 7 and 72. The same potential, having passed through the element OR NOT 75, enters the reset input of the counter 66 and keeps its outputs in zero state nii. The input 140 of block 8 receives information in a serial code from the output 102 of receiver 1 (Fig. 146), which is accompanied by clock pulses at the input L1 (Fig. 14c).

Operation of block 8 is resolved when the potential is switched. At input 142 of the block to one state (Fig. 14a), then counter 66 switches over each pulse at input 141 (Fig. 14b) provided that single information bits arrive at block input 140 . Single information bits increase the content of the counter 66 by one. As with the AND 69 element, the unit levels of the input signal coincide with the clock pulses at the input 141. Moreover, any zero bit of the input information, having passed through the element NOT 74 to the element IS-NOT 70 and after coinciding with the clock pulse, enters through the element OR 75 to the reset input of the counter 66 and sets its outputs to the logical zero state. Thus, the counter counts only the consecutive units in the input information and is reset when any zero information bit appears in the input sequence of units. Figures 14g, d, e show the discharge outputs of counter 66.

The state of the outputs of the counter 66 is constantly analyzed by the decoder 67 and in the case of counting five consecutive units, a zero level appears at its output (Fig. 14g), which enters the information input of the trigger 68 and is gated along its control input by the nearest clock signal. impulse from input 141. As a result, the direct output of the trigger 68 switches to the zero state (Fig. 14h), thereby prohibiting the passage of clock pulses through the AND 73 element, since the resolving potential, previously received from the And 71 output, is removed ( fig.14i) cher of an OR gate 76. The passage of the clock pulse through AND gate 73 can then be permitted if

0

five

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five

0

five

0

five

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five

the next received information bit at input 140 is one. However, if it is equal to zero, as shown in fig. 14b, then the zero potential enters the input of element AND 72 through its output (fig. 14 k) and the element OR 76 (fig. 14l) passes to the input of element AND 73, prohibiting the passage of a clock pulse at its output (fig.14m).

As a result of the operation of block 8, the removal of bit-stuffing to a clock sequence removes the pulses which are. the second follow five individual bits of the information bits. Since these pulses from the output of the bit-stuffing remover block shift information in the receiving registers of block 4, the absence of these pulses at such moments leads to the fact that the information in these registers does not shift and the zero bits representing bit stuffing, not registered in registers, i.e. bit staffing removed

The bit-stuffing addition unit 20 solves the inverse problem: it adds to the transmitted information, which is not control, zeroes after each subsequent sequence of five units. The restrictions on the encoding of the transmitted information, which can be any, are removed, and the control characters are easily decrypted at the receiving end, since they differ from any other transmitted information in that they contain more than five units in their composition.

The timing diagram of the operation of the bit stuffing addition unit 20 is shown in FIG. The bit-adding unit 20 operates as follows. In the initial state. The switching of the counter 88 is prohibited by the zero potential from the input 187 of the unit 20 (Fig. 15a). At input 189, unit 20 is transferred. intended for the transmission of information (Fig. 156), and to the input 188 — the transmission clock pulses (Fig. 15c) from the output 106 of the synchronization unit 3.

When a single permitting potential arrives at input 187 (Fig. 15a), the counter 88 is able to count the subunits in the input information, giving the result of the count to its code outputs (Fig., F). If among sub-: p d reaching information bits wind 23

594550

zero, the counter resets to the initial state and the counting starts anew. This happens until the counter has counted up to five further single bits. This combination of counter outputs is detected by the decoder 89, which has a zero potential at its output (; FIG. 15g). The closest front of the clock-ij-o pulse trigger 90 sets- 4 to the zero state and blocks the passage of the next clock pulse through the element And 93. As a result, the output sequence 1 turns off the pulses going after the thirtieth next information bits (FIG. 15i). This achieves the same effect as with the operation of the bit-stuff removing unit 8. However, if in the first case, the remote pulses do not shift the information to the 5 receiving registers, and this means that they do not carry accepted bit stuffing zeros, then in this case there is no shift pulse on the clock input. 173 1 of the register 1 7 of the transmission leads to the fact that instead of the missing next bit from register 17 in its place there is a zero bit through the element 24, and the remaining bits from register 17 are transmitted after inserting bitstuffing.

The single-vibration 31 (Fig. 16) is a conventional single-shot with reset and restart, implemented on the basis of a K 155 AHS chip. The reset input is not used, and both start inputs (direct and inverse) are used for their intended purpose.

Formula

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. 1. A device for inter-subscriber communication with a communication line, comprising a receiver, a transmitter, a synchronization unit, a register block, a decoder block, a memory block, a first counter, a block-removing unit, a receive control block, the first element D, the first the OR element, the first, second and third triggers, the receiver input being the line input of the device, and the output connected to the informational 5 inputs of the bit stuffing removing unit, the register unit and the recording input of the synchronization unit mode, the first output of which is connected to the clock input. om transmitter whose output

20 is a linear output of the device, the second output of the synchronization unit is connected to the write-write gating input of the memory unit, the first enable input of the decoder unit, the 25th input of the receive control unit, the first synchronous input of the registering unit, the enable input of which is connected to the resolution enable input of the first counter, the R input of the first trigger and the output of the second trigger, and the output of the bit-removal removing unit is connected to the clock input of the first counter, the strobe lock input the reception control unit and the second clock synchronized input of the register unit, the first output of which is connected:, to the first input of the first OR element, the second, third and fourth outputs are connected to the first, second and third information inputs of the decoder local loop, and the third information input is connected with the first data input to the block by input 223 one-shot vibrator memory, the fifth output of the register block is connected to the serial information input of the reception control block, the output of which is connected to the first input The first element is And, the reset input is connected to the output of the first trigger, the second input of the first element is And, and the input of the initial installation of the memory block, the first write input of which is connected to the first output of the first counter, the read input and the second write input of the memory block are subscriber device inputs and records, the first output of the memory block is the subscriber data output

35

40

one time, at the moment when 213 trigger 27 is set to single state. This is a direct one-shot input, which in the course of further operation is JX-Bc as allowing as long as the potential from the 213 flip-flop output 27 is present.

On input 224, the one-shot works in all other cases, that is. on all triggering pulses from the output 167 of the counter 15, through the inverse input, through which the one-shot is triggered by the negative edge of the counter 15 pulse.

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formula

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device, and the second output is connected to the R input of the third trigger, the output of which is the subscriber output of the device receiving request, the S input of the third trigger is connected to the second input of the first SH and the output of the first I, the third input of which is connected to the first output ka decoders, the second output of which is connected to the S-input of the first tri-. The third and fourth outputs of the decoder unit are connected respectively to the S- and R-inputs of the second trigger, the second data input of the memory block being the subscriber input of the device data, characterized in that, in order to expand the functionality of the device by providing two-way data exchange between any subscribers of the ring system in accordance with the exchange protocol adopted, the second counter, command register, transmission register, control character register, transmission control block, bl to add bit-stuff, second and third elements OR, second, third and fourth elements AND, fourth, fifth and sixth, seventh and eighth triggers and one-shot, with the first input of the second element AND connected to the output of the first element OR, and the second input - with the release of the fourth trigger ,. S-input of the first flip-flop, with the enable input of the second counter, the write input of the register of control C4v4s and the enable input of the bit stuffing addition block, and the output of the second element AND are connected to the first input of the second element OR, the output of which is connected to the information the transmitter input, and the second input is connected to the input of the third element I, the first input of which is connected to it with the clock inputs of the second counter of the register of control characters, the register of the transmission - with; 1 way of blocking the strobe of the control unit and transmitting Odom block bittaffinga addition, the clock input of which the first output soeinen sinhroizatsii block write clock input Lok memory warning light and the clock input of the transmission unit, the information lok.dobavleni bit-stuffing, podklyuen .vtoromu entry to the third element and the output of the third OR gate, per30

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the second input is connected to the outputs of the register of control characters, the second input is connected to the output of the transmission control unit, and the third input is connected to the output of the transmission register and the information input of the transmission control unit, the reset input of which is connected to the output of the sixth trigger and the R input of the seventh trigger, the output of which is connected to the R-input of the fourth trigger and the input of the shift resolution of the register of control characters, and the S-input is connected to the output of the eighth trigger and the R-input of the sixth trigger, whose S-input is connected to the output of the fifth trigger, input p A resolution of the fifth trigger, to the first input of the single-vibration and D-input of the eighth trigger, the synchronous input of which is connected to the output of the second counter and to the second input of the single-vibration, the output of which is connected to the input of the reading strobe of the memory block and the input of the recording strobe, transfer register , the information input of which is connected to the first output of the memory unit, the second output of which is connected to the R input of the fifth trigger, the subscriber input of the device data is connected to the information input of the command register, and the control input of the recording direction and reading the memory block data is connected to the first output of the command register, the strobing input of which is connected to the subscriber input of the device, the second output of the command register is connected to the second resolution enable input of the decoder unit, and the third code is connected to the first input of the fourth AND element, the output of which is connected to the S-input of the fourth trigger and the third input of the second OR element, and the second input is connected to the fifth output of the decoder unit.

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2. The device according to claim 1, characterized in that the block of adding bit-stuffing contains the first and second elements AND, the element NOT, the first element AND-NOT, the counter, the decoder and the trigger, and the first input of the first element AND is connected to the input of the element NOT and is a serial information input of the block, the first input of the first element IS-NOT is the input of the resolution of the operation of the blot, the synchronous input of the trigger is connected to the first input of the second element AND,

and the first input of the second element IS-NOT and with the second input of the first element AND is the clock input of the block, the output of which is connected to the output of the second element AND, the second input which is connected to the output of the trigger 1) —the input of which is connected to the output decoder, information, the inputs of which are connected to the parallel inputs of the counter, the push input of which is connected to the output of the first AND element, and the reset input to the output of the first NAND element, the second input of which is connected to the output of the second AND NAND element, The entrance is: o connected to the input element is NOT.

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Claims (3)

Claim  1. A device for interfacing between subscribers with a communication line containing! receiver, transmitter, synchronization unit, register unit, decoder unit, memory unit, first counter, bit stuffing remover unit, reception control unit, first element C, first element OR, first, second and third triggers, the receiver input being linear the device input, and the output is connected to the information inputs of the bit-stuff removal unit, the register block and the write input of the synchronization block mode, the first output of which is connected to the clock input of the transmitter, the output of which is the line output of the device, the second The output of the synchronization block is connected to the gating input of the memory block recording, the first enable input of the decoder unit, the clock input of the reception control unit, the first synchronized input of the register unit and the synchronous input of the bitstaffing removal unit, the enable input of which is connected to the counting enable input of the first counter, K-input of the first trigger and the output of the second trigger, and the output of the bitstaffing removal unit is connected to the clock input of the first counter, the gate lock input of the reception control unit and to the second clock synchronous input ohm register block, the first output of which is connected .. to the first input of the first element OR, the second, third and fourth outputs are connected respectively to the first, second and third information inputs of the decoder unit, the third information input of which is connected to the first data input of the memory block, the fifth output the register block is connected to the serial information input of the reception control block, the output of which is connected to the first input of the first element I, and the reset input is connected to the output of the first trigger, the second input of the first And, and the input of the initial installation of the memory block, the first write input of which is connected to the first output of the first counter, the read input and the second write input of the memory block are subscriber inputs and records of the device, the first output of the memory block is the subscriber data output ²⁵ 1594550 device, and the second output is connected to the I-input of the third trigger, the output of which is the subscriber output of the request to receive the device, the δ input of the third trigger is connected to the second input of the first element OR and the output of the first element AND, the third input of which is connected to the first output of the block decoders, the second output of which is connected to the 8-input of the first trig. Hera, and the third and fourth outputs of the decoder unit are connected respectively to the 8 and I inputs of the second trigger, the second data input of the memory block 15 being the subscriber data input of the device, characterized in that, in order to expand the functionality of the device by providing 20 bilateral data exchange between any subscribers of the ring system in accordance with the adopted exchange protocol, the second counter, command register, transmission register 25 is entered into it chi, control character register, transmission control block, bit-stuffing addition block, second and third elements OR, second, third and fourth elements AND, fourth, fifth and sixth, seventh and eighth triggers and one-shot, with the first input of the second element AND connected with the release of the first element OR, and the second input - with the release of the fourth trigger ,. 8-input of the fifth trigger, with the input of the resolution of the account of the second counter, the input of the recording of the register of control shafts and the permission of the operation of the block for adding bit-stuffing, and the output of the second element AND connected to the first input of the second element OR, the output of which is connected to the information input of the transmitter, and the second input is connected to the input of the third element I, the first input of which is connected to the clock inputs of the second counter of the register of control characters, the transmission register - with the input of the gate blocking of the transmission control unit and from add bit block one ¹ staffing, the clock input of which is connected to the first output of the synchronization block, the synchronization input of the memory block recording and the clock input of the transmission control block, the information block, adding bit stuffing. Connected to the second input of the third element AND and the output of the third element OR, per45 26 the second input is connected to the outputs of the register of control characters, the second input is connected to the output of the transmission control unit, and the third input is connected to the output of the transmission register and the information input of the transmission control unit, the reset input of which is connected to the output of the sixth trigger and the I input of the seventh trigger, output which is connected to the input of the fourth trigger and the input shift enable register of control characters, and 8-input connected to the output of the eighth trigger and I-input of the sixth trigger, 8-input of which is connected to the output of the fifth trigger, the input solutions of the fifth flip-flop, a first input odnovibra30 35 40 50 55 torus and ϋ-input of the eighth trigger, the sync input of which is connected to the output of the second counter and the second input of the one-vibrator, the output of which is connected to the input of the strobe of the memory block and to the input of the strobe of the transfer register, the information input of which is connected to the first output of the memory block, the second the output of which is connected to the I-input of the fifth trigger, the subscriber input of the device data is connected to the information input of the command register, and the input of the direction of writing and reading the data of the memory block is connected to the first output register commands whose gate input is connected to the subscriber input of the device, the second output of the command register is connected to the second enable input of the decoder unit, and the third output is connected to the first input of the fourth And element, the output of which is connected to the 5th input of the fourth trigger and the third input the second element is OR, and the second input is connected to the fifth output of the decoder unit. 2. Device pop. 1, characterized in that the block for adding bit-stuffing contains the first and second elements AND, the element NOT, the first element NAND, the counter, the decoder and the trigger, the first input of the first element AND connected to the input of the element NOT and is the serial information input of the block, the first input of the first element AND-NOT is the input of the permission of the blog to work, the synchronous input of the trigger is connected to the first input of the second element AND, 1594550 and the first input of the second element IS-NOT and with the second input of the first element AND is the clock input of the block whose output is connected to the output of the second element AND, the second input..Which is connected to the output of the trigger 1) - the input of which is connected to the output of the Decoder, information the inputs of which are connected to the parallel inputs of the counter, the clock input of which is connected to the output of the first AND element, and the reset input to the output of the first AND-NOT element, the second input of which is connected to the output of the second AND-NOT element, the second input of which is connected to the input m element is NOT. 1 1594550 Fig.Z 15945.50 Fig.Ch FIG. five 1594550 1594550 Fig.8 Flag opening Address Information Check sequence Flag closing End of frame / frame. accepted OHSHO I byte Variable length 2 bytes OHSHO ΙΙΙΙΙΙΟΟ 9 1594550 ar 6G ABOUT 1594550 1594550 η_τ --— ί-ΰ — ц_гь_1 · D | 1111111111111111 ...... 111111111 “Π-1 ι. Π. ι ~ ι π η. . π π π ... π ..... 3 ΓΉ ΓΉ ι t "'t" · ι · ι · LH - ...... 3 . . L-Τ ' and ....... G ^{- C} 1.P I 1 I 1.1 11111) 1_111 Ι Ι) ι 111 11 ι ι ι FIG. 15