SU1578660A1 - Apparatus for measuring shaft rotational speed - Google Patents

Abstract

The invention relates to a measurement technique, in particular, to devices for measuring non-electric quantities by electrical methods, and can be used to measure the rotational speed of shafts in tests of agricultural machinery. The goal is to increase the reliability of the device due to the automatic monitoring of sensor performance. The pulses of sensors 2 and 3 through the element OR - NOT 13, the element AND - NOT 21 and the inverter 14 set the first binary two-bit counter 18 to "1"

if the first sensor 2 is healthy, then the pulses from its output through the first element AND - NOT 15, the driver 16, the element OR - NOT 17 set the first binary two-digit counter to "0". If the first sensor is faulty, then the counter 18 is installed in the base "2", which causes the failure indicator 20 to light up and the state of the counter 18 locks. The second sensor is monitored in the same way. 1 il.

Description

The invention relates to measuring equipment, in particular to a device st-? you to measure non-electric quantities by electric methods, and can be used to measure shaft speed during agricultural machinery tests.

The aim of the invention is to increase reliability, jq

The drawing shows a functional circuit of the device.

The device comprises a gear steel disk 1 mounted on a rotating shaft, a first measuring transducer'2 mounted near a disk with a working gap between the teeth and the core of the transducer, a second measuring transducer 3 mounted with a shift of 180 ° along the drive: relative to the first measuring transducer, the first 4 and second 5 amplifiers, generator. 6 reference frequency, frequency divider 7, selector 8, binary decimal counter 25 chik 9, memory register 10, decoder 11, digital display unit 12, first, last element OR NOT 13, first inverter-14, first element And -NOT 15, the first reset pulse generator 16, the second OR-NOT 17 element, the first binary two-bit counter 18, the second inverter 19, the first LED failure indicator 20, the second NAND 21 element, the third 22, the fourth 23 inverters, the third AND element -NOT 24, second reset pulse shaper 25, third element OR-NOT 26, second binary two-digit counter ir 27, sixth inverter 28, second LED failure indicator 29, fourth element NAND 30, fifth inverter 31 and third reset pulse generator 32,.

The output of the first measuring transmitter 2 is connected to the input of the first amplifier 4, and the output of the latter with the first input of the first element ORINE 13 and with the input of the first inverter

14, The output of the first inverter is connected to the first input of the first NAND element

15, The output of the last one is connected to the input of the first shaper 1 6, the input of which is connected to the first input of the second element OR NOT 17. The output of the last one is connected to the R-input of the first counter> 18, the output of which is connected to the input of the third inverter 22, The output of the third inverter connected with the input of the first LED indicator 20, with the first input of the second element AND 21 and the second input of the first element. that AND-NOT 15, The output of the second element AND-NOT connected to the input of the second inverter 16, the output of which is connected to the C-input of the first counter 18, and the output of the second measuring transducer 3 is connected to the input of the second amplifier 5, The output of the second amplifier is connected to the second input the first element OR-NOT 13 and with the input of the fourth inverter 23, the output of the latter is connected to the first input of the third element AND-NOT 24, the output of which is connected to the input of the second driver 25, the output of the last connected to the first input of the third element OR-NOT 26, the output of which conjoined is connected with the R-input of the second counter 27. The output of the second counter is connected to the input of the sixth inverter 28, the output of which is connected to the input of the second LED indicator 29, to the first input of the fourth element AND-NOT 30 and the second input of the third element AND-NOT 24, the output of the fourth AND-NOT element 30 is connected to the input of the inverter 31, the fifth inverter output is connected to the C-In of the second counter 27. In this case, the output of the first OR-NOT 13 element is connected by the second inputs of the second 21 and fourth 30 AND-NOT elements and with the first input selector -8. The input of the third driver 32 is connected to the second output of the frequency divider 7, and the output to the second inputs of the second 17 and third 26 elements SH1I-NOT. The output of the reference frequency generator 6 is connected to the input of the frequency divider 7, the first output of which is connected to the second input of the selector 8 and the second input of the memory register 10, and the second output is connected to the R-input. binary decimal counter 9, the output of the selector 8 is connected to the C-input of the binary decimal counter 9, the output of which is connected to the first input of the memory register 10. The output of the latter is connected to the input of the decoder II, and the output of the decoder is connected to the input of the digital indication unit 12.

The device operates as follows.

When the gear disk 1 rotates, voltage pulses appear at the outputs of the first 2 and second 3 measuring transducers, which amplify. They are the first 4 and second 5 amplifiers ⁵ 1578660 to the operating signal levels of the logic elements. In the absence of violations and the functioning of the input channels of the device, voltage pulses corresponding to a logic level of 0 are applied to the inputs of the first OR-NOT 13 element, from the output of which pulses of logic level 1 are fed to the first input of selector 8, to the second input of which a logic level gate 1 s the first output of the frequency divider 7, from the output of the selector a series of pulses (with a duration of the series T = 1C) is fed to the counting input of the binary decimal counter 2 <ica 9, preset in state 0 at the R-input of pulses and from the second output of the frequency divider 7. After the series of pulses has been written to the counter, the information should be rewritten into the memory register 10 by the trailing edge of the strobe pulse from the output of the frequency divider 7 at the second input of the memory register. The decoder 11 converts the binary-decimal code into a seven-segment code necessary for operation of the digital indication block 12, and there is a digital indication of the result of measuring the speed.

At the same time, logical 0 pulses from the output of the amplifiers are fed to the inputs of the first 14 and fourth 23 inverters.

The logical 1 pulse from the output of the first OR-NOT 13 element is supplied to the second inputs of the second 21 and fourth 30 AND-NOT elements, and since the first, 18th and second 27 counters are preset to the state ”0 with a reset pulse from the second output of the divider frequency 7 through the third driver of the reset pulse 23 and the second inputs of the second 17 and third 26 elements OR NOT at the R-inputs of the counters, at the first inputs of the second and fourth 30 elements AND NOT set the logic level 1, from the outputs of these elements through the second 19 and fifth 31 inverters at C-inputs counter a blunt edge pulse condition 1. rows whose first 15 AND-NO comrade also cal 1, the logical pulses I ¹ from the outputs of the first 14 and the fourth inverter 23 to a first input 27 and poslogicheskoy 1, rear translates counters Since in the second third vhoi 24 elements - $$ set log level!

of the first 15 and second 24 AND-NOT elements, from the outputs of which logical zero pulses are fed to the inputs of the first 16 and second 25 shapers, which generate reset pulses with a delay after the end of the pulse at their inputs, Counters 18 and 27 again go into state 0, LED failure indicators 20 and 29 are extinguished, which signals the normal functioning of both input channels (including measuring transducers, amplifiers, and signal transmission lines). In this case, pulses of the longest duration are received at the input of the selector (from the first or second measuring transducer) from the output of the first element OR NOT 13, If the functioning of the first input channel is malfunctioning (for example, an unacceptable increase in the working gap due to the weakening of the fastening of the first measuring transducer), the pulse from the output of the second measuring transducer 4 through the amplifier 5, the first the OR-NOT 13 element is fed to the input of the selector 8 and to the second inputs of the AND-NOT elements 21 and 30. Since the binary counters 18 and 27 are pre-set to state 0 from the second output of the frequency divider 7 through the third shaper 32 and the elements OR-NOT 17 and 26, and at the first inputs of the elements AND 21 and 30 the logical level 1 is set from the outputs of the counters 18 and 27, respectively, through inverters 22 and 28, from the outputs of the elements AND-NOT 21 and 30 through inverters 19 and 31, a logical 1 pulse is fed to the C-inputs of the first 18 and second 27 binary counters. The counters are set to state 1. Due to the fact that the first input channel is in a failure state, the logical 0 pulse does not arrive at the input of the first inverter 14 , logical impulse 1 does not go to the first input p of the first AND-NOT element 15, a logical 0 pulse does not go to the input of the first driver 16, a logical zero pulse does not go to the first input of the second OR-NOT 17 element, to R ··· - the input of the first counter 18 does not receive a reset pulse and the first counter remains in state 1, since the input of the fourth inverter 23 simultaneously received a logical 0 pulse; from the output of the fourth inverter 7, the logical 1 ”pulse arrived at the first input of the third AND-NOT 24 element, the logical pulse from the output of the third AND-NOT element 24 0 entered the input of the second formiro STUDIO 25 reset pulse. From the output of the second shaper, the first input of the third element, OR NOT 26, received a logic 0 pulse delayed relative to the trailing edge of the input pulse, and it was received to the R-input of the second counter 27. drank a reset pulse, the second counter is set to 0 '\ When a second pulse is received from the output 55 of the second measuring transducer 4 and there is a failure of the first input measuring channel, the pulse propagation process is repeated, the first counter 18 is set to state 2, the second counter 27. sequentially is set to states 1 and 0 ”, in this case, from the output of the first counter, the logical 1” signal is fed to the input of the third inverter 22, the output of which the logical 0 signal is fed to the input of the first LED Nogo indicator 20 occurs flashing signal failure of the first input channel. The signal of a logical O ”from the output of the third inverter 22 is also fed to the second input of the first, first AND-NOT 15 element and to the first input of the second AND-NOT 21 element, which ensures the storage of the failure signal in the first counter 18 (state 2 '!) with a cycle Тц = 2С from the body 7 of the frequency of the extender 32, the element OR NOT of the counter, If no, the working conditions of the elements remain. it the same, and there is a signaling failure of the first input channel. The device works similarly. When a failure occurs on the second input <· measuring channel, In these cases.

the readings of the device are considered reliable, and after the end of the measurement process, the faulty input channel must be repaired. With alternate or simultaneous operation of the failure indicators, the measurements are stopped .. and the device needs to be repaired.

Claims (1)

The formula of the invention before the arrival of the discharge pulse from the second virgin soil output the input of the third, handicap then through the second 17 on the H input of the first situation was not a failure · A device for measuring the frequency of rotation of the shaft, containing a gear first, second and third element counter, a decoder, so as to ensure the reliability of the device, the first and second amplifiers, geopore frequency, a divider -. 25 steel disc, first and second sensors, you And, more often introduced nerator, selector, memory register, digital display, first, second and third elements OR NOT, first, second, third, fourth, fifth and sixth inverters, first and second binary two-digit counters, first, second and third reset pulse shapers, first and second ', failure indicators, fourth element NAND,. than the second sensor is mounted 180 ° round the disk circumference relative to the first sensor, the output of the horn is connected to the first amplifier, the first inverter, the first AND-NOT element, the first reset pulse generator, the second OR-NOT element, the first binary two-bit core, the third inverter and the first failure indicator, the second sensor is connected to series-connected second I eye amplifier; the fourth inverter, the third AND-NOT element, the second reset pulse generator, the third OR-NOT element, the second binary two-bit core, the sixth inverter. by a torus and a second failure indicator, the output of the third inverter is connected to the second input of the first AND-NOT element, and the first input of the second AND-NOT element, the output of which through the second inverter ι is connected by a removable input of the first binary two-bit counter, the output of the sixth inverter is connected to the second input the third element AND NOT and the first output of the fourth element; AND NOT, the output of which through the fifth inverter is connected to the counting input of the second binary two-digit counter, the output of the first and second amplifiers are connected respectively to the first I and the second inputs of the first OR-NOT element, the output of which is connected to the second inputs of the second and fourth AND-NOT elements and connected in series with a selector, counter, register, decoder and digital display unit, the output of the reference frequency generator is connected to R through a frequency divider -input of the counter and with the input of the third reset pulse shaper, you ^J 1578660 10 stroke of which is connected to the second input- “the second input of the selector and the second input of the second and third elements OR register. NOT, the second output of the divider is connected to