SU1569973A1 - Mis-transistor-base pulse shaper - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital devices on MOS transistors for controlling the amplitude of pulses, for example, in control devices for charge transfer devices in CMD BIS. The purpose of the invention is to provide electronic adjustment of the amplitude of the output pulses with low power consumption and high reliability of operation. The achievement of the effects indicated in the target is due to the possibility of adjusting the threshold voltage of the load transistor 2 of the MIS inverter by switching its substrate to the control bus 11 (positive control voltage) for the open state and to the common bus 13 (the lowest potential) for the open state . The driver contains active and load N-channel transistors 1 and 2, inverter 3, first and second keys 4 and 5, first, second and third delay elements 6, 7 and 8, input and output buses 9 and 10, control bus 11, bus 12 power, common bus 13. 3 Il.

Description

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The invention relates to a pulse technique and can be used in digital devices on MOS transistors for controlling the amplitude of pulses, for example, in control devices for charge transfer devices in CMD BIS.

The purpose of the invention is to provide electronic adjustment of the amplitude of the output pulses with low power consumption and high reliability of operation.

FIG. 1 shows a structural electrical circuit; - pulse generator; in fig. 2 - time diagrams of signals; in fig. 3 - an example of the implementation of a shaper on a CMD inverter.

The driver (Fig. 1) of the pulses contains an active n-channel transistor 1, a load n-channel transistor 2, an inverter 3, the first key 4, the second key 5, the first delay element 6, the second delay element 7, the third delay element 8, the input bus 9, output bus 10, bus, control 11, power pin 12 and common bus 13.

Transistors 1 and 2 are connected successively between buses 12 and 13, forming an inverter whose output is connected to the output bus 10. The gate of the load transistor 2 is connected to the output of the first front delay element 6 connected by the input through inverter 3 to the input bus 9, and through the second element 7 of the front delay to the control input of the first switch 4. The gate of the active transistor 1 is connected to the input bus 9 through the element 8 of the delay. The load transistor 2 substrate is connected via the first switch 4 to the control bus 11 and, via the control input connected to the input bus 9, the second switch 5 to the common 13. The drain of the active transistor 1 and the source of the load transistor 2 are connected to the output bus 10.

The pulse shaper operates as follows.

In the initial state, a high level signal is applied to the input bus 9 (Fig. 2a), a high level signal is applied to the gate of the active transistor 1 through the front delay element 8, and a low level signal is sent to the gate of the load transistor 2 (Fig. 26 ), key 4

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through the front delay element 7, a high level control signal is applied, the key 4 is closed. The key 5 is opened by a high level control signal from the input bus 9, and a low level signal is applied to the substrate of the load transistor 2. The open state of transistor 1 and the closed state of transistor 2 determine the presence of zero potential, a common bus on the output bus 10 (Fig. 2c, e), and the open state of key 5 and the closed state of key 4 cause the presence of zero potential on the substrate of the load transistor 2 (Fig. 26).

After the voltage on the input bus 9 decreases to zero, the transistor 1 is locked and the key 5 is opened. Transistor 2 opens later due to the delay of the pulse at the output of inverter 3 by element 6. The signal on the input bus 9 is inverted by inverter 3. The front the output signal from the inverter 3 is delayed by delay element 6. At the source of transistor 2, the minimum value of the high level of the output voltage corresponding to the maximum reverse bias of the p – n junction is set to the substrate — the source of transistor 2 and, consequently, to its maximum threshold voltage. Later, with a delay determined by the element 7, the switch 4 is closed, and the voltage across the substrate of the transistor 2 increases and becomes equal to the voltage on the control bus 11. The reverse bias on the pn-junction substrate - the source of the transistor 2 and its threshold voltage decrease, which leads to an additional increase in the voltage level on the output bus 10. In the case that the highest voltage on the bus 11 does not exceed the maximum possible voltage level on the output bus 10, corresponding to the voltage on the pn-junction substrate - the source of transistor 2, at which its threshold voltage is minimal, this transition is always locked when the front of the output pulse is formed on the output bus 10. Amp ituda this pulse depends on the voltage established on the control bus 11. I

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pulse will cause the key 5 to close. A drop without a delay is transmitted from the output of the inverter 3 through the front delay element 6 to the gate of the load transistor 2 (Fig. 2b) and through the front delay element 7 to the substrate of the load transistor 2 (Fig. 2c) In this case, the load transistor 2 closes on the gate, and on the substrate of the transistor 2 a signal decay is formed and the potential of the common bus 13 is established. Fixing the substrate of the load transistor 2 by the most negative potential of the circuit increases the reliability of the device operation in eloom.

The signal front from the input bus 9 is transmitted to the gate through the front delay element 8. torus 1. Active tran. rr. 1 is enabled and on the output bus. 10 fsr. Pulse decay. Since the unlocking of transistor 1 occurs later, with a delay determined by delay element 8, the p – n junction substrate — the source of transistor 2 remains locked when the pulse decays on bus 11.

In this case, a sequence of signals is provided to the gates of transistors 1 and 2 and the control inputs of switches 4 and 5, at which the p – n junction substrate — the source of transistor 2 never shifts in the forward direction. Due to this, the thyristor effect, which reduces the reliability of MIS integrated circuits, is excluded.

Changing the voltage on the control bus 10 connected to the substrate of the loading transistor 2 when the active transistor 1 is ejected, you can adjust the amplitude of the output pulses by spending the minimum power needed only to recharge the MIS transistors.

The flipper, implemented using a CMOS inverter (FIG. 3), contains n-channel active transistor 1, a load transistor 2, a two-input OR-NOT logic element, consisting of transistors 14-17, the first inverter consisting of transistors 18 and 19, the second inverter, consisting of transistors 20 and 21, the third inverter, consisting of transistors 22 and 23, the fourth

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an inverter consisting of transistors 24 and 25, a first n-channel transistor 26, a second n-channel transistor 27, a first key consisting of transistors 28 and 29, a second key consisting of transistors 30 and 31, an input bus 9, output bus 10, bus 11 — control, power bus 12, common bus 13.

The pulse shaper operates as follows.

In the initial state, if there is a high level signal on the input bus 9, a low level signal is set at the output of the first inverter (transistors 18 and 19) and at the output of the third inverter (transistors 22 and 23), a high level signal is output at the second inverter ( transistors 20 and 21) and the fourth inverter (transistors 2A and 25). The load transistor 2 is closed by a low level signal fed to the gate of transistor 2 from the output of a two-input logic element OR NOT (transistors 14-17). The substrate of the transistor 2 through open transistors 26 and 27 is connected to the common bus 13 and disconnected from the bus 10 controlling the closed first key (transistors 28 and 29) and the closed second key (transistors 30 and 31). The potential of the output bus 10 is equal to the potential of the common bus 13. When a low level signal is applied to the input bus 9, the first, second, third and fourth inverters are connected in series. In this case, transistor 1 is first closed by a low

level from the output of the second inverter, opens the transistor 2 to the high level signals from the two-input logic element OR NOT, then the voltage from the control bus 11 is applied to the substrate of the load transistor through the opening first and second switches. The magnitude of the control voltage determines the magnitude of the high level output signal on the output bus 10.

When a high level signal is fed to the input bus 9, the substrate of the transistor 2 is first connected

to the common bus 13 through the transistor 26. At the same time, the substrate of the transistor 2 is disconnected from the control bus 11 when the transistors 28 and 29 of the first key are closed. Transistor 2 closes the gate with a low signal

the level from the output of the two-input logic element OR NOT, after which the transistor 1 is opened by a high level signal from the output of the second inverter, and a low level signal appears on the output bus 10.

Receiving the Electronic Capability

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adjusting the amplitude of the output pulses due to the use of the switching circuit of the substrate of the load transistor 2 to the control bus 11 (positive regulated voltage) for it. horned state -fs nor to the common bus 13 (the lowest potential) for the closed state.

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In addition, the included first, second, third, and fourth inverters, the two-input element OR NOT, the first and second n-channel transistors, the first and second keys provide the order of signals to the gate of the active transistor 25, the gate and the substrate of the load transistor, preventing the displacement of the pn-junction drain - the substrate of the load transistor in the forward direction, and the ignition in the integral MIS-microscope of the parasitic transistor. This ensures high reliability of the driver.

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Claims (1)

Invention Formula MOSFET pulse generator containing an active n-channel MOS transistor connected by a source and a substrate to a common bus, a load n-channel MOS transistor connected by a drain to a power bus, a source to an output bus and a drain of an active p-channel MOS -transistor, and the gate through the inverter - to the input bus, characterized in that, in order to provide electronic adjustment of the amplitude of the output pulses with low power consumption and high reliability in operation, the first key connected between the control bus With the load transistor substrate, the second switch connected between the load transistor substrate and the common busbar, the first edge delay element connected between the inverter output and the gate of the load transistor, the second edge delay element connected between the output of the first edge delay element and the control input of the first key, the third front delay element connected between the input of the device and the gate of the active transistor; the control input of the second switch is connected to the input bus. Fzg.2