SU1555888A1 - Ring packet information transmission network - Google Patents

Abstract

The invention relates to information and computing technology. The purpose of the invention is to increase the amount of information transmitted by allowing simultaneous transmission of information packets by all stations of the network in one time window. For this, the ring packet data transmission network contains stations 1, each of which has a transceiver 2, consisting of a receiver and transmitter of a receipt, an interface unit, a recording unit, a transmitter and a clock synchronization unit, and an access unit 3 consisting of a distributor, generator receipt, delay node, receipt decoder, decoder, key, reception, transmission, recording and issuance registers, accumulator, address sensor, encoder, control signal generator, sync combination generator and decoder. When the network is operating, a packet of information transmitted by the sending station 1 is received by the destination station 1 after a certain number of time windows have expired, equal to the number of stations 1 located between them, at which this packet is received. 1 tab., 3 Il.

Description

1

ka and clock synchronization unit, and access unit 3 consisting of a distributor, receipt generator, delay node, receipt decoder, decoder, key, reception, transmission, recording and output registers, accumulator, address sensor, encoder, control signal generator, generator sync and descrambler. During network operation, a packet of information transmitted by the station-sender 1 is received by the destination station 1 after a certain number of time windows has expired, equal to the number of stations 1 between them at which this packet is received. 1 tab., 3 Il.

The invention relates to a technique of information and computer systems, data transmission systems using a packet transmission method, and can be used to create high-performance local communication networks of distributed systems.

The purpose of the invention is to increase the amount of transmitted information by allowing simultaneous transmission of information packets by all stations of the network in one time period.

Figure 1 shows the structural electrical circuit of the proposed network; 2 is a structural electrical circuit of the transceiver and the access unit; FIG. 3 is a structural electrical circuit of a control signal generator.

The ring packet data transmission network contains stations 1, each of which contains a transceiver 2 and an access block 3. The transceiver contains a receiver 4 receipts, block 5 inquiry, block 6 registration, transmitter 7, transmitter 8 receipts and block 9 clock synchronization.

The access unit 3 contains the distributor 10, the generator 11 of the receipt, the delay node 12, the decoder 13 of the quantification, the decoder 14, the key 15, the reception register 16, the accumulator 17, the transfer register 18, the register 19, the address sensor 20, the issuance register 21 to

The core 22, the control signal generator 23, the synchronization generator 24 and the decoder 25. The control signal generator comprises a counter 26, the first 27, the second 28, the third 29, the fourth 30, the fifth 31, the sixth 32, the seventh 33, the eighth 34, the ninth 35, tenth 36 and eleventh 37 triggers, first 38, second .39, third 40 and fourth 41 elements OR NOT, first

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the second 42, the second 43, the third 44, the fourth 45, the fifth 46 and the sixth 47 elements AND, the fifth element of the IPI-NE 48, the register 49 and the permanent storage node 50.

The network works as follows.

At the start of work, phasing is performed on a cycle. For this, one of the stations 1, which is the main one, transmits the sync pattern from the sync pattern generator 24 via the transmitter 7 to the forward link. In this case, the keys 15 at all stations 1, except the main one, are in the closed state. From the forward link of the sync combination at each station 1 through the interface unit 5 and the registration unit 6 enters the address and sync combination flag decoder 25 and simultaneously through the delay node 12 and the closed key 15 to the transmitter 7 to transmit it to the next station 1.

Thus, the sync pattern goes through all stations 1 and returns to the main one. The decoder 15 of the flag, address and sync pattern of each station 1, when received in sync pattern, generates a signal for setting into the appropriate phase and triggering the distributor 10 time window, which forms time intervals of equal duration - time windows -} at the beginning of which station 1 is allowed to send and receive packets information.

Upon completion of phasing over the cycle by a signal from the distributor 10 time windows, the key 15 at all stations is transferred to the open state, therefore the exchange of information packets in the network during one time window occurs only between neighboring stations 1. At that, for each transmitted packet the station

1 should receive a confirmation signal — a receipt —y which is received on the reverse communication channel from the neighboring station 1. From this, the corresponding time window duration is chosen equal to the time interval from the beginning of the packet transmission on the forward channel to the next station 1 until the end of reception on the reverse link of the receipt. Thus, a packet of information transmitted by station 1 by the sender is received by station 1 after a certain number of time windows, equal to the number of stations 1 located between them, at which the package is received.

The storage capacity of the storage unit 17 allows simultaneous storage of up to four packets of information. The joint operation in the multiplexing mode of the reception register 16, accumulator 17, transfer register 18, register from subscriber 19, address sensor 20, and issuance register 21 to the subscriber ensures simultaneous parallel recording of information packets 17 in two cells of the memory communication, the other from the subscriber) and reading from the other two memory cells of the accumulator 17 information packets (one to the direct communication channel, the other to the subscriber). The multiplexing is effected by signals from the control signal generator 23, which, in addition, generates the necessary read and write signals for accumulator 17 and generates signals of the state of the memory cells, according to which the address sensor 20 generates the addresses of the necessary memory cells of the accumulator 17 selected for write and read packets of information from them.

The mechanism for transmitting information packets over a network is as follows.

The packet from the subscriber at the beginning of the time window enters through the encoder 22 and the recording register 19 from the subscriber to the accumulator 17. In the next time window, this packet from the accumulator 17 through the transmission register 18, the transmitter 7 is transmitted on the forward link 3 to the next station 1, to which it arrives through the block 5 of the conjugation, the block 6 of registration in the decoder 25 flags, addresses and sync

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and a delay unit 12 in which there is a delay of time equal to the duration of the transmission of the service portion of the packet (the flag and the address of the destination station). In the decoder 25 (the flag, the address and the sync pattern are analyzed by the service part of the packet. From the output of the delay unit 12, the received packet arrives through the decoder 14 and the receive register 16 to the accumulator 17. In the absence of errors in the received packet, the decoder 14 generates a signal for and 11 receipts, from the output of which the receipts through the transmitter 8 of the receipt are transmitted by reverse call to the station 1 to the sender, to which it goes through the receiver 4 of the receipt to the decoder 13 of the receipt.

Upon receipt, the shaper 23 of the control signals of station 1 of the sender performs 25 sent packets, informs the subscriber about the successful transmission of the packet and allows it to issue the next packet. In the absence of errors in the received packet, the driver 23 of the control signals of station 1 of the recipient in the next time window, if the packet is intended for this station 1, controls the delivery of the packet to the subscriber (from the accumulator 17 through the issuance register 21 to the subscriber), and otherwise - controls the transmission of the packet to the next station 1. If an error is detected in the received packet, then no receipt is issued for it, while the control station 23 of the control station 1 of the recipient clears the received packet with an error. If there is no receipt for the transmitted packet of station 1, the sender in the next time window carries out its retransmission.

The control signal generator 23 at the eleventh and twelfth outputs generates signals for reading and writing to accumulator 17} at the first output, allowing the output from the receive register 16 to the first inputs of the accumulator 17 of the next 55 byte received from the information channel of the packet and allowing the output from the address sensor 20 to the second inputs of the drive 17 of the address at which this byte follows zz-

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write to drive 17; at the second output, a signal allowing the issuance from the register 19 of a record from the subscriber to the first inputs (information bus) of the accumulator 17 of the next byte received from the subscriber of the packet, and allowing the output from the address sensor 20 to the second inputs (address bus) of the accumulator 17 to which this byte should be recorded in the drive 17: at the third output, a signal by which the register from the subscriber 19 begins receiving a packet from the subscriber and by which in the address sensor 20 begins the formation of the memory address of the memory 17, into which the packet tons of subscriber should be recorded; on the fourth, fifth, sixth and seventh outputs, the status signals of the first subscriber, second subscriber, first transit and second transit cells of the memory 17, respectively; at the eighth output of the signal, by which the address sensor 20 detects its own or transit packet, comes from the information channel of communication; at the ninth output, a signal allowing the output from the address sensor 20 to the second inputs (address bus) of the accumulator 17 of the address of the next byte of the packet read to the subscriber and allowing reception of this byte received on the first outputs (data bus) of the accumulator 17 into the output register 21 to subscriber; at the tenth output, a signal allowing the output from the address sensor 20 to the second inputs (address bus) of the accumulator 17 of the next byte of a packet read into the information channel of communication and allowing the reception of this byte, arriving at the first outputs (information bus) of the accumulator 17, in the register 18 of the transfer; on the thirteenth output a signal allowing the subscriber to transmit his packet to the station; at the fourteenth output, a signal by which the subscriber determines that the station received a packet for it. The beginning and end of the formation of signals at the eleventh, twelfth, first, second, ninth and tenth outputs are determined by the signals at the beginning of the time window and the end of the time window, respectively, arriving at the third and fourth inputs of the form

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bodies 23 control signals. The signal at the fourteenth output is formed by the start of the time window signal, provided that the previous time window received its packet from the information channel (the subscriber responds to this signal with the receive signal K, the control signals 23 and the twelfth input of the address sensor 20, and which begins the issuance of a packet from the drive 17 to the subscriber). Signals at the third and thirteenth outputs are generated by the Transmission Request signal received at the beginning of the time window from the subscriber to the ninth input of the control signal generator 23 provided that the second subscriber cell of the memory 17 is free. The signal at the eighth output is generated by the signal at the fifth input of the driver 23 of the control signals received from the first output of the decoder 25. The signals of the state of the memory cells of the storage device 17 are generated at the fourth, fifth, sixth and seventh outputs by the signal End of the time window that arrives at the fourth input of the driver 23 control signals.

The signals of the state of the memory cells in the current time window are determined by the signals of the state of the memory cells and the signals on: the sixth, (Flag signal from the output of the decoder 25), the fifth (signal Own packet or Transit packet from the first

0 output of the decoder 25), the seventh (signal Error or No error from the first output of the decoder 14), the eighth (signal of the Receipt or Receipt not from the output of the decoder 13

5 receipts, the ninth (signal from the subscriber Transmission request and the second (signal from the subscriber is ready to receive) inputs of the former 23 control signals in the previous time window. Counter 26, triggers 34-37, elements OR NOT 38-41, AND 43 -45 and 47 are used to form the signals at the eleventh, twelfth, first, second, ninth and tenth outputs, the signal from the output of the IPI-NE 39 terminal being fed to the eleventh output, the signal from the fourth output of counter 26 to the twelfth output output signal

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element 46 is the first output, the signal from the output of element 47 is the second output, the signal from the output of the element 45 is the ninth output, and the signal from the output of the element 44 is the tenth output of the control signal generator 23.

A trigger 27 is used to form a signal. A packet is received at the fourteenth output of the control signal generator 23. If in the previous time window a packet was received from the information channel of a communication, the signal of the state of the first subscriber memory cell at the output of DO 4 of the permanent storage node (ROM) 50 has a single level. This signal arrives at the D-input of the trigger 27. By the signal of the beginning of the time window, a single-level signal is generated at the output of the flip-flop 27, which is fed to the fourteenth output of the control signal generator 23. According to the signal End of the time window, the signal of the state of the first user cell of the memory (since the packet was read to it from the subscriber) at the output of the DOU ROM 50 will take the zero level and go to the D-input of the trigger 27. By the next signal The beginning of the time window at the output of the trigger 27 a zero signal is generated.

The trigger 32, the elements of AND 42 and ORIDA 48 are used to form the signals Enable transmission and Record packet from the subscriber, respectively, at the thirteenth and third outputs of the driver 23 control signals. If the second subscriber cell is free in the previous time window, the signal at output D03 of ROM 50 is zero. This signal is fed to the input element IPI-NE 48, from the output of which a signal of a single level is received. This signal opens the key executed on AND 42. Now if the subscriber issues a Transmission Request signal to the ninth input of the control signal generator 23, this signal passes the I 42 element and from its output enters the trigger input of the trigger 32 and the third output of the imager 23 control signals. The trigger 32 in this case generates at its output a signal of a single level, which is fed to the trinadz 5888810

the output of the driver 23 control signals. On the End of time window signal, the signal at the output of flip-flop 32 is reset and (since the packet from the subscriber was recorded in this time window) the state of the second subscriber memory cell is changed.

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The trigger 29 is used to form a signal of its own packet or a through packet at the eighth output of the control signal generator 23. At the same time, a single signal level corresponds to the reception of its own packet, and zero - to a transit packet. The permanent storage node 50 is used to form at its outputs D00, DO ,, 00g and D03 signals of the state of the memory cells in accordance with the ten-bit word of the state of the station, which is fed to its inputs AO-A9. 5 Register 49 is used to store this station state word, which by the signal End of the time window (coming from the fourth input of the control signal generator 23 to its A input) is recorded from its inputs D10-D1 to the register 49 and arrives at the outputs D00-D0g. The first four bits of the station state word are formed by signals of the memory cell received at the inputs D1Q-Dt, register 49. Moreover, the output of the D00 ROM 50 receives the signal of the state of the first transit memory cell, and the output DO. the second Q of the transit memory cell, from the output 00 of the first subscriber cell of the memory and from the DO output - the second. subscriber memory cell. The unit signal level of the cell state corresponds to the fact that the cell is occupied, and the zero level to the fact that the cell is free. The remaining six bits are formed at the outputs of triggers 28-33. At the output of the trigger 28, a single level signal is generated by the Flag signal at the sixth output, and a zero level signal by the End time window signal. Thus, the input of the D14 register 49 receives a single-level signal, if a flag has been received, and a zero-level signal otherwise. At the output of the trigger 29 on the signal twelve

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The output of the control signal generator 23 generates a unit-level signal, and a signal at the end of the time window produces a zero-level signal.

Thus, the input of the W register 49 receives a single level signal, if the address has been decrypted

of its packet, and the signal of the zero VER-JQ You are at station 1 and is realized in the middle if the address of the transit packet has been decrypted. At the inverse of the trigger output 30, a signal of a unit level is generated at the eighth input at the receipt signal, and at the end of the time signal

window

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zero signal.

End of time ok. Zero level. So

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Thus, a single level signal arrives at the D1e input of the registry 49 if an error-free transmission of the packet to the information communication channel was carried out, and a zero-level signal if there was transmission by error. At the output of the trigger 31, the signal from the subscriber is received To receive the second level signal from the subscriber 23, a single level signal is generated, and the signal to the signal

Thus, the input of the D17 register 49 receives a single-level signal if the packet has been read to the subscriber, and the zero-level signal otherwise. At the output of the trigger 32, a signal from a subscriber is sent to the Transmission Request. A single level signal is generated at the ninth input of the generator 23, and a zero level signal is received at the End Time Window signal.

Thus, at the input of D1. register 49 receives a single-level signal if a packet has been recorded from the subscriber, and a zero-level signal otherwise. At the inverse output of the trigger 33, an error signal is not present at the seventh input of the imaging unit 23, a single level signal is generated, and a signal at the end of the time window is a zero level signal.

Thus, a single-level signal arrives at the input of the D1-register 49 if there is no error in the received packet and a zero signal, if an error is detected in the received packet. The station state word in the previous time window, arriving at inputs D1C - D1 of register 49 and at the signal End of time window at

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A-input coming from the outputs D00 DO. register 49 to inputs AO-A9 of ROM 50 is used to form memory cell status signals for the current time window. The correspondence of the signals of the states of the memory cells to the input words of the state of the station is determined by the adopted algorithm

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The firmware table for ROM 50. ROM 50 has a volume of 4096 bits and an organization of 1024 words 4 bits. The firmware table shows only

162 station status words, resolution by the station operation algorithm. The remaining words are forbidden (they cannot be formed at the inputs of AO-A9) and therefore it does not matter what will be recorded at the addresses that match the forbidden words. For an example of forming the signals of the states of the memory cells, consider the row 151 of the firmware table. Since in the previous time window, the first transit cell contained a packet for transmission (the signal at the AO input is 1) and as a receipt was received at the information channel of the packet transmitted in this time window (the signal at the A6 input is 1), then the current time window first transient cell status signal

memory must be changed from zan

then do

on Free (output signal 0 is set to 0). So

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as in the previous time window, the first transit cell is occupied, and the second transit cell is free (the signal at output A1 is 0) and since it was. the arrival of a packet to the station from the information channel of communication (the signal at the A4 input is 1) with a transit address (the signal at the A5 input is 0) and its reception without errors (the signal at the A9 input is 1) is fixed, then in the current time window the signal is neither the second transit cell of the memory should be changed from Free to Zan (signal at output D0 (set to 1).

Since, in the previous time window, the first subscriber memory cell contained its packet for issuing to the subscriber (the signal at input A2 is 1) and since the signal from subscriber K was received (signal at input A7 is 1), it is

In the time window, the state signal of the first user cell of the memory should be changed from Zanto to Free (the output signal B0g is set to 0). Since in the previous time window, the second subscriber cell is free (the signal at input A3 is 0) and since there was a signal from the subscriber

The transfer request (the signal at input A8 is 1), then in the current time window, the signal of the state of the second subscriber cell must be changed from Free to Zan (the output signal BOS is set to 1). Similarly, all 162 rows of the firmware table are obtained.

Claims (1)

Invention Formula A ring packet information transmission network containing stations serially connected in a ring, the information inputs and outputs of which are information inputs and outputs of the network, each station containing a transceiver and an access unit whose first and second signal outputs are combined with the first and second signal inputs of the transceiver, the first, second and third signal outputs of which are connected respectively to the first, second and third signal inputs of the access unit, and the channel The input and output of the transceiver are the channel inputs and outputs of the station, the information inputs and outputs of which are the information inputs and outputs of the access unit, which contains a receipt generator, a delay node, a receipt decoder, a decoder, a key, a drive, an encoder, a decoder, the distributor, the synchronization combination generator and the reception register, whose outputs are connected to the first inputs of the accumulator, the output of the delay node is connected to the first input of the key, the second input of which is connected to the first output of the distributor, the output of which is connected to the first input of the decoder, the second input of which is connected to the first input of the delay unit, the second input of which is connected to the first input of the receipt generator, to the first input of the decoder, to the first input of the receive register, 0 5 0 Q s o, five to the third input of the decoder and to the first input of the receipt decoder, the second input of which is the first signal input of the access unit, the second and third signal inputs of which are respectively the first and second inputs of the delay node, the first and second signal outputs of the access unit are respectively the generator output a receipt and an exit key, the transceiver comprising a transmitter, a clock synchronization unit, a registration unit and an interface unit, the output of which is connected to the first input of the clock unit and the first input of the registration unit, the second input of which is connected to the first output of the clock synchronization unit, the second output of which is connected to the first input of the transmitter and is the third signal output of the transceiver, the second signal output of which is the output of the registration unit, the second input of the transmitter is the second signal input of the transceiver, the channel output and input of which are respectively the output of the transmitter and the input of the interface block, characterized in that, in order to increase the Removing the transmitted information by simultaneously transmitting packets by all stations of the network in one time window, the additional channel input of the previous station is connected to the additional channel output of the subsequent station, and a recording register, transmission register, address sensor, output register and signal conditioner are entered into the access unit. control, the first output of which is connected to the second input of the receive register and the first input of the address sensor, the second input of which is connected to the first run of the write register and to the second The output of the control signal generator, the third output of which is connected to the second input of the write register and the third input of the address sensor, the fourth input of which is connected to the fourth input of the decoder and the fourth output of the control signaling generator, the fifth, sixth, seventh and eighth outputs of which are connected respectively To the fifth, sixth, seventh and eighth inputs of the address sensor, the ninth input of which is connected to the first input of the output register and to the ninth output of the control signal generator, ten The th output of which is connected to the first input of the transmission register and the tenth input of the address sensor, the outputs of which are connected to the second inputs of the accumulator, the first inputs of which are connected to the outputs of the record register, the third input of which is connected to the output of the encoder, the first input of which is connected to the eleventh input of the address sensor to the fourth input of the register of the record, to the first input of the distributor, to the first input of the sync generator, to the second input of the issuing register, to the second input of the transmission register, to the second input of the node The holders and to the first input of the control signal generator, the second input of which is connected to the twelfth input of the address sensor, the thirteenth input of which is connected to the third input of the control signal generator and to the third output of the distributor, the fourth output of which is connected to the fourth input of the control signal generator, the fifth input of which connected to the first output of the decoder, the second output of which is connected to the fourteenth input of the address sensor, with the third input of the receive register and with the sixth input is formed L control signals, a seventh input coupled to a second input of the generator, and a receipt to the first output of the decoder, a second input of which with five The single output of the distributor is connected to the second input of the synchronization generator, the output of which is connected to the key output and to the output of the transfer register, the third inputs of which are connected to the outputs of the storage device and the third inputs of the output register, the second output of the decoder is connected to the fourth input of the reception register, the output of the receipt decoder is connected to the eighth input of the control signal generator, the eleventh and twelfth outputs of which are connected respectively to the third and fourth inputs opitel, the third output of the decoder is connected to the second input of the distributor, while the second input of the encoder, the first, second and ninth inputs of the control signal generator are the information inputs of the access unit, the information outputs of which are the thirteenth and fourteenth output signals of the control signal generator and output of the issue register, and the receiver of the receipt and the transmitter of the receipt are entered into the transceiver, the first input of which is connected to the second output of the clock synchronization unit and to the first input of the receiver The receipt, the second input of which is an additional channel input of the transceiver, the additional channel output of which is the output of the transmitter of the receipt, the second input of which is the first signal input of the transceiver, the first signal output of Q is the receipt receiver output. 0 five