SU1547033A1 - Device for monitoring memory units - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to monitor the correct functioning of RAM on integrated circuits. The aim of the invention is to increase the reliability of the control under external conditions. The device contains a clock pulse generator 1, an address counter 2 connected in series and an auxiliary counter 3, a test signal generator 6, a comparison element 4 comparing the input and output data of the monitored memory node. The output of each K-th digit (where K = 1.2 ... M) of the address counter is connected to the contact pad for connecting the (M-K + 1) -th digit of the monitored memory node. The device quickly scans the largest parts of the memory node, which provides greater reliability in monitoring short-term failures in the memory node under external conditions, when the spatial region formed by the charged particle is more than one simple element of the memory node, but smaller than the size of such elements. such as a memory chip. 1 il.

Description

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The invention relates to automation and computer technology and can be used to monitor the correct functioning of RAM on integrated circuits under external conditions.

The purpose of the invention is to increase the reliability of monitoring the memory nodes under external conditions.

The drawing shows a structural diagram of the proposed device.

The device contains a clock pulse generator 1, an address counter 2 auxiliary counter 3, a comparison element 4, the output of which is the control output 5 of the device a test signal generator 6, a clock pulse generator 1 output connected to the control input of the comparison element 4 and the counter counting input 2 addresses, the transfer output of which is connected to the counting input of the auxiliary counter 3, the outputs of which are connected to the inputs of the test signal generator 6, the outputs of which are connected to contacts 7 for connection information inputs of the monitored memory node 8 and with the first group of inputs of the comparison element 4, the second group of inputs of which is connected to contacts 9 for connecting the information outputs of the memory node 8, input 10 of the write / read permission of which is connected to the output of the clock generator 1, the output of each The K-th (where K 1,2, ... M) bit of the counter 2 address is connected to the contact pad for connecting the (M-K + 1) th bit of the monitored node 8 of the memory.

The device works as follows.

A monitored memory node is connected to the contact pads. The test pulse generator provides the formation of a constant frequency pulse sequence. With a single value of the signal at the output of the generator 1, the reading of information from the monitored memory node 8 is enabled, as well as the operation of the comparison element 4. If the information at the outputs of the monitored memory node 8 coincides with the information at its information inputs, the comparison element 4 generates a signal of no error at the output 5 of the device. If the information does not match, then

An output is generated indicating an error. On the falling edge of the signal from the oscillator 1 clock pulses switching the counter 2 addresses. After this, the state of the output signal does not change until a new value of the logical unit appears at the output of the clock generator, since the operation of the comparison element is blocked and the memory node is in the recording mode. The implementation of the comparison element can be different, for example, it can be implemented on the EXCLUSIVE OR elements, whose inputs form the first and second groups of inputs of the comparison element, and the outputs of the EXCLUSIVE OR elements are not connected to the inputs of the OR element, the output

which is connected to the first input of the element IS-NOT, the second input of which is the control input of the comparison element, the output of the element IS-NOT is the control output of the device.

The device, in its operation, most often changes the state of the higher address bit of the memory node, and the frequency of changes of each previous bit will be two times less than this. This provides a quick search through the largest parts of the memory node. In other words, at each control tick, a new state of the decoder and memory bank is analyzed, if the memory node has an organization in the form of banks, or the control of the new chip is provided, if the memory node includes several chips, or the memory cell from the new group is monitored memory cells if the memory node is a large integrated circuit.

In this way, a quick review of the sequence of elements forming the memory node is carried out, each of which is a collection of the most closely spaced and electrically connected electronic components. This provides greater confidence in the control of short-term failures in the operation of the memory node in the conditions of external influences, when the action of the charged particle leads to

the formation of a spatial region in which pro failure is broken, the size of which is greater than one simplest

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element of the memory node, but less than the size of elements such as, for example, a memory chip.

Claims (2)

Claims An apparatus for monitoring memory nodes, comprising a clock pulse generator, an address counter, an auxiliary counter, a test signal conditioner, and a reference element whose output is the control output of the device, the clock pulse output is connected to the control input element. the counting input of the address counter, the transfer output of which is connected to the counting input of the auxiliary counter, the outputs of which are connected to the inputs of the test signal generator, the outputs of which They are connected to the first group of inputs of the comparison element and are information outputs of the device for connecting the information inputs of the monitored memory node; the inputs of the second group of the comparison element are information inputs of the device for connecting information outputs of the monitored memory node, characterized in that, in order to increase the reliability of the control under external conditions, the output of each K-th (where K 1. 2 ... M) the bit of the address counter is connected to the (M-K-I) th digit of the address of the monitored memory node (where M is the number of bits of the address inputs of the monitored memory node)