SU1538253A1 - Digital frequency synthesizer with frequency modulation - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to increase speed. The synthesizer contains a reference gr 1, a modulating signal source 2, a phase modulator 3, an integrator 4, controllable attenuators 5 and 18, a phase detector 6, a signal source 7 tuning, elimination-OR 8 and 19, a sampling-storage unit / BVH /, 9, 10 low-pass filter, frequency divider 11 with variable coefficient. division, frequency setting unit 12, A / D converter 13, pulse subtraction unit 14, shift register 15, memory register 16, controlled by rc 17 and compensating signal source 20. At the first stage of the work, the installation of blocks on the specified parameters is carried out. At the second stage of the tuning mode, the phase-locked loop (PLL) of the initial frequency detuning occurs. In this case, the PLL operates offline. In the third stage in the adjustment mode, the deviation of the phase difference in the PLL from the stationary value is reduced to zero. The synthesizer switches from tuning mode to normal mode. The goal is achieved by the introduction of a BVH 9, a subtraction unit 14 and a source of 20. 2 Il.

Description

tiki). The duration of this stage is K adjustment intervals T0 (Fig. 2a and k).

At the third stage of the tuning mode of the proposed digital frequency synthesizer, the attenuation coefficient A4 of the second controlled attenuator 18 is set, which ensures the required quality of the frequency modulation of the output oscillation of the synthesizer. For undistorted frequency modulation, the attenuation factor A.

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the unit enters the first input of the first element 8 and, together with the logical zero signal arriving at the second input of the first element 8, results in a logical unit signal at the output of the first element 8. The signal of the logical unit received at the control input of the source of the setting signal 7, turns it on and, entering the control input of the pulse subtraction unit 14, blocks the passage of the DCPD 11 output pulses, starting from (K + 1) -th, to the input of the block 9 (Fig. 2 and). The blocking of the clock pulses of the sampling-storage unit 9 is necessary for opening the PLL at the time of introduction of disturbances into the system. As a result, on the leading edge of the K-th output pulse of the PDCD 11, an amplitude voltage drop arrives at the control input of the UG 17 from the tuning signal source 7

X0 (Fig. 2g). This difference leads to a deviation of the phase difference of the signals arriving at the inputs of the PD 6 from the stationary value by the time the next (K + 1) th pulse appears at the output of the PDKD 1I. The magnitude of this deviation of the phase difference from the stationary value is determined by the additional phase shift during the time interval T0 of the signal fed to another PD input 6. This additional phase shift of the output signal of the PDDK 11 is due to the modulation of the oscillation frequency of the UG 17 by the x0 drop (input to control UG 17) and is equal to x = 8 g. Tft / n.

logical units in the (K + 1) -th bit of this register 6 (Fig. 2d). The appearance of the signal of the logical unit at the second output of the register 15 leads to the switching of the output signal of the second element 19 from the signal of the logical zero to the signal of the logical unit (Fig. 2e). The signal of the logical unit is fed to the control input of the register 1 6 and enables the recording of the code z arriving at the information input of the register 16 by a positive differential formed on the second output 15 of the A / D converter 13 at the time of the completion of the formation of the code z. As a result, the code z KAU) I.x

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-0-mg / "is fed to the control input of the second controlled attenuator 18. The attenuation factor A ,, of the second controlled attenuator 18 is associated with the code received at its control input, by the following relationship: A" U / K0 (where Y is the code,

control input, and K0 is the attenuator transmission coefficient at). Therefore, when setting the control code Y z and choosing K0 F x0T0S, the attenuation coefficient A of the second controlled attenuator 18 becomes

30 equal to the value required for undistorted modulation, i.e. Ag.

Simultaneously with the resolution of recording the measurement result of the value of A corresponding to the undistorted modulation,

35, the signal of the logical unit, arising at the second output of register 15, produces the following commutation of the source of the perturbation of the PLL system.

Signal source 7 is turned off.

40 settings, since the measurement of the required value A. has already occurred, and the disconnection is carried out by a logical zero signal fed to the control input of the signal source 7

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By the time of the appearance of the (K + 1) th pulse at the output of the DPCD 11, the phase difference of the signals arriving at the PD 6 inputs deviates from the stationary value of the mean value -x6S r-T0 / N. The phase difference deviations of the output voltage of the PD 6 corresponding to this deviation from the stationary value are x0S rT0 / N (where Uw is the amplitude of the output voltage of the PD 6, and T1 is the slope of its normalized discriminatory characteristic)

The (K + 1) th DPKD output pulse 11, entering the input of the start of the A / D converter 13, starts the process of converting the analog voltage generated at the output of the FD 6 as a result of the readout of 45 settings from the output of the first element 8.

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logical units in the (K + 1) -th bit of this register 6 (Fig. 2d). The appearance of the signal of the logical unit at the second output of the register 15 leads to the switching of the output signal of the second element 19 from the signal of the logical zero to the signal of the logical unit (Fig. 2e). The signal of the logical unit is fed to the control input of register 1 6 and enables the recording of the code z arriving at the information input of register 16 by a positive differential formed on the second output 5 of the A / D converter 13 at the time of the completion of the formation of the code z. As a result, the code z KAU) I.x

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-0-mg / "is fed to the control input of the second controlled attenuator 18. The attenuation factor A ,, of the second controlled attenuator 18 is associated with the code received at its control input, by the following relationship: A U / K0 (where Y is

control input, and K0 is the attenuator transmission coefficient at). Therefore, when setting the control code Y z and choosing K0 F x0T0S, the attenuation coefficient A of the second controlled attenuator 18 becomes

0 equal to the value required for undistorted modulation, i.e. Ag.

Simultaneously with the resolution of recording the measurement result of the value of A corresponding to the undistorted modulation,

5, the signal of the logical unit arising at the second output of register 15 produces the following commutation of the source of perturbation of the PLL system.

Signal source 7 is turned off.

0 settings, since the measurement of the required value A. has already occurred, and the disconnection is carried out by a logical zero signal fed to the control input of the source 7 signal

5 settings from the output of the first element 8.

phase arising at the time of the appearance of this pulse. At the input of the ADC 13 there is an inverting buffer follower with a corresponding separator capacitor, therefore on its register 15, since the first input

digital output 7 is formed at the output. proportional to the deviation of the output voltage of the PD 6 from the stationary value, taken with the opposite sign, i.e. z Kau, nUwF x0T0-S r / N (where K atsp is the conversion coefficient of the A / D converter 13). In addition, the (K – H) th DPKD output pulse 11. arriving at the input of the register g, advances the signal

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The first element 8 already receives a logical unit signal from the first output of register 15.

The signal of the logical unit, arising at the second output of register 15, arriving at the control input of the source 2 of the modulating signal, includes this source, since the process of exposing the required modulation

A logical zero signal results from acting on the second input of the first element 8 of a logical one signal occurring at the second output.

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The first element 8 already receives a logical unit signal from the first output of register 15.

The signal of the logical unit, arising at the second output of register 15, arriving at the control input of the source 2 of the modulating signal, includes this source, since the process of exposing the required modulation

the attenuation coefficient of the attenuator 18 in the synthesizer is almost complete and you can switch to the modulation mode.

The signal of the logical unit that occurs at the second output of the register 15, includes the source 20 of the compensating signal. The supply of a compensating signal (disturbance) is necessary to compensate for the deviation of the phase difference in the PLL system, which occurs under the influence of the setting signal source 7, which supplied the control of the UG 17 with a voltage drop of amplitude x0 and a duration of one adjustment interval T0 (Fig. 2g). The source 20 of the compensating signal is turned on by the signal of the logical unit, which is fed to its control input from the output of the second element 19, since the output of the second element 19 as a result of the appearance of the logical unit at the second output of the register 15 of the signal of the logical unit the output of register 15, allowing the closure of the PLL, which is open after the appearance of the signal of the logical unit at the first output of the register 16.

The closure of the PLL system is produced by the signal of the logical unit that occurs at the output of the first element 8 and arrives at the control input of the pulse subtraction unit 14. The signal of the logical unit occurs at the output of the first element 8 as a result of the second input of the signal of the logical unit at the second output of the register 15. As a result, for all the output pulses of the PDKD 11, starting with (K + 2) -th, blocking the clock impulses of block 9 sampling storage is canceled and the PLL is closed again. The (K + 2) th output pulse of the DPCD 11, entering the input of register 15, advances the signal of the logical unit to the (K + 2) th discharge of this register, which causes the iHa to appear in the third output of the register 15 of the | jia logical units. The signal of a logical unit, acting on the first input of the second element 19, switches its output signal to a signal of logical zero, since the signal of a logical unit also arrives at the second input of the second element 19 from the second output of the register 15. Output

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the signal of the logical zero of the second element 19, arriving at the control input of the register 16, prohibits the recording of new information in this register. In addition, the logical zero signal from the output of the second element 19 falls on the control input of the source 20 of the compensating signal and turns it off.

Source 20 of the compensating signal, turned on by (K + 1) th DPK 11 output pulse and turned off (K + 2) th pulse, supplies to the UG 17 control input voltage -h0 for the duration of one adjustment interval T0 (Fig. 2h) . The effect of this voltage leads to a deviation of the phase of the signal arriving at the other input of PD 6 from the output of the DPDK 11, at the time of the appearance of the (K + 2) th output pulse of the PDKD 11 by the value T0 / N, i.e. by an amount that compensates for the deviation under the action of a test disturbance introduced from the source 7 of the tuning signal.

As a result, the total deviation of the phase difference from the stationary value in the PLL system at the time of the appearance at the output of the DPCD 11 (K + 2) -th pulse is almost zero. The presence of a non-zero residual deviation of the phase difference in the system can only be due to the imperfect operation of the sampling-storage unit 9 and the inaccuracy of compensation of the setting signal x0 from the source 7 of the tuning signal compensating disturbance -x0 from the source 20 of the compensating signal.

The third stage of operation of the proposed frequency synthesizer in the tuning mode ends with the appearance of a (K + 2) -th pulse at the output of the DPCD 11 and its duration is two times T0 of the adjustment interval of the PLL system. By the end of this stage, the measurement of the attenuation coefficient A 2 of the second controlled attenuator 18, corresponding to the undistorted modulation, ends and the measurement result is stored in register 16. The phase difference in the PLL from the stationary value to the end of this stage is practically reduced to zero.

The source of modulating signal 2 is switched on by the end of the third stage of the roaming mode, and the frequency synthesizer will intermix with the end of this stage

from tuning mode to normal operation, which continues until the frequency setting unit 12 issues a command to change the frequency of the output oscillation of the frequency synthesizer with frequency modulation.

Claims (1)

Invention Formula A frequency modulated digital synthesizer containing a series-connected source is connected to another input of the phase modulator, the output of the first element is EXCLUSIVE OR connected to the control input of the tuning source, the output of the second controlled attenuator is connected to the control input of the controlled generator, the output of the second element EXCLUSIVE OR is connected to the control input of the memory register, the output of which is connected to the control input of the second control attenuator, characterized in that to increase signal, the first controlled t5 relationship, entered sequentially attenuator, integrator, phase modulator and phase detector, serially connected low-pass filter, controlled oscillator, frequency divider with variable division factor 20 and shift register, the first, second and third outputs of which are connected to the first input of the first element EXCLUSIVE OR, respectively the connected pulse subtraction unit and the sampling-storage unit, as well as the source of the compensating signal, the signal input of the sampling-storage unit connected to the output of the phase detector, and the output of the sampling-storage unit to the input of the low-pass filter, the output of the first element SPARKER OR connected with manager the second input of the first element is the EXCLUSIVE house of the pulse subtraction unit, also OR, and the first input of the second element is EXCLUSIVE OR, the reset input of the shift register is connected to the control input of the first controlled attenuator and the control input of the dividers of frequency bodies with a variable division factor and connected to the output of the frequency setting unit, the second input of the first element EXCLUSIVE OR is connected to the control input of the source - ,, - as the modulating signal and the second input of the second element EXCLUSIVE OR, another input of the phase detector The pa is connected to the input of the start of the analog-digital converter and connected to the output before the frequency divider with a variable division factor, the reference oscillator The input input of which is connected to the output of a frequency divider with a variable division factor, the output of the first controlled attenuator is connected to the input of the second controlled attenuator, the output of the second element EXCLUSIVE OR is connected to the control input of the source of the compensating signal, the output of which is connected to the output of the tuning source and to the control input of the controlled oscillator, the output of the phase detector is connected to the signal input of the analog digital converter, the first and second outputs of which are connected respectively etstvenno with the information and the clock inputs of the memory register. connected to another input of the phase modulator, the output of the first element EXCLUSIVE OR is connected to the control input of the source of the tuning signal, the output of the second controlled attenuator is connected to the control input of the controlled generator, the output of the second element EXCLUSIVE OR is connected to the control input of the memory register, output which is connected to the control input of the second controlled attenuator, which is different from the fact that, in order to improve speed, they are introduced in series the connected pulse subtraction unit and the sampling-storage unit, as well as the source of the compensating signal, the signal input of the sampling-storage unit connected to the output of the phase detector, and the output of the sampling-storage unit to the input of the low-pass filter, the output of the first EXCLUSIVE element OR connected to the control input of the pulse subtraction unit, also The input input of which is connected to the output of a frequency divider with a variable division factor, the output of the first controlled attenuator is connected to the input of the second controlled attenuator, the output of the second element EXCLUSIVE OR is connected to the control input of the source of the compensating signal, the output of which is connected to the output of the tuning source and with control input of the controlled oscillator, the output of the phase detector is connected to the signal input of the analog digital converter, the first and second outputs of which are connected respectively etstvenno with the information and the clock inputs of the memory register.  ft / (M (MM L .pULTUJI J -itt -Xe t FIG. 2