SU1529290A1 - Memory unit - Google Patents

Abstract

The invention relates to computing and can be used in the construction of universal nodes of digital computers. The aim of the invention is to increase the reliability of the operation of the memory block. This goal is achieved by introducing selectors 4, 7, comparison blocks 6.8, failure analysis block 9, DV flip-flop 5, which provides for replacing the failed memory block and generating a failure signal. 2 Il.

Description

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The invention relates to computing technology and can be used to build universal nodes of digital computers.

The aim of the invention is to increase the reliability of the operation of the block by introducing into its logical structure means of functional control and restoration of working capacity.

Pa Fig, 1 is a block diagram of a memory block; in fig. 2 — DV trigger and device comparison block, exemplary embodiment.

The storage unit contains DV-register 1, RS-trigger 2, element NO 3, first selector 4, DV-trigger 5, first comparison unit 6, second selector 7, second comparison unit 8, failure analysis unit 9, informational inputs 10 of the unit , inputs of mode 11, synchronization 12, reset 13, information output 14 of the block. Outputs failure 15 and partial failure 16 block.

The DV trigger and block comparison block contain (Fig. 2) D-trigger 17, RS trigger 18, NOT elements 19 and 20, AND-II element 21, NOT 22 and 23 elements, AND-OR-NOT 24 element.

The direct and inverse outputs of D-flip-flop 17 and RS-flip-flop 18 are the inputs of the element 24, the outputs of the group of elements that form the time delays of the signals Un C are connected to the synchronization inputs of the element 24, the output of which fails to the input of the same block in order to capture information from failure.

The memory unit operates in two ways: the information recording mode and the information storage mode.

In the information recording mode, a logical signal is present at the input 11 of the block, a write pulse is present at the input 12, and information that needs to be written into the memory block is present at the D inputs 10.

The operation and control of the right-hand BifflHHTHT triggering of the triggers 17 and 18 is performed as follows.

When the trigger 17 of the positive edge of the sync signal appears on the sync input, its state is transferred to the element 24..

The control of the correct response is performed by a comparison signal from the output of element 24, which is formed after the response time

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elements 19-21. When the DV trigger is properly triggered, a signal Failure at the output of the comparison unit will be generated. Otherwise, i.e. if there is a malfunction in the DV trigger, the first or second group of inputs of the element 24 will work, at its output a logical unit signal will be generated, which through the fifth group of inputs will fix

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signal failure, providing a steady state logical unit at its output.

If the information is written to the triggers of register 1 correctly, then the logic unit signaling the failure of the corresponding trigger failed to appear on any of the outputs of block 6 of the comparison.

In this case, the first groups of inputs of the selector 7 will be opened, the signals

E at the inputs are zero. Consequently, the values of the signals at the direct outputs of the register triggers go to the corresponding information outputs of the block.

In case of failure of any trigger in register 1, a single signal appears at the output of comparison block 6 Failure, which opens the second group of inputs of the selector 7 and, also entering the selector 4, opens the group of its information inputs, thus preparing the chain of recording information that failed trigger register 1 to trigger 5. This ensures that the failed trigger of register 1 is automatically replaced by trigger 5, and output 16 of the block

9 analysis of failures on Wits signal Partial failure.

From the outputs of the selector 7, the output of the block will receive information from the register 1 without the declining bit (signals E are zero) and trigger 5, replacing the second input of the selector 7 that failed (the signal E of this bit is equal to one). In the event of a failure of more than one block trigger, due to the absence of the necessary reserve, a Failure signal is generated at output 15,

The operability control of the trigger 5 is carried out similarly to the control of the bits of the register 1 using the comparison unit 8. In the event of a malfunction of this trigger block

failure analysis will signal a partial block failure.

Thus, by introducing an additional trigger, as well as a selector, comparison units, and a failure analysis block with appropriate connections, the replacement of the failed memory block is replaced, which increases the reliability of the block.

Claims (1)

Invention Formula DV-register D inputs, the V-input of which is connected to the V-input of the PU-flip-flop and the sixth inputs of the comparison units, the fifth inputs of which are combined and are the reset input of the memory unit, and the fourth inputs of the comparison comparison block. - DV-register input, information outputs of which are connected to the second input of the first comparison unit and the first information input of the second selector, the second input of which is connected to the first DV trigger output and a second input Memory unit containing a DV register, 5 second comparing unit, first input the NOT element and the RS flip-flop, the output of which is connected to the V-input of the register, the C-input of which is connected to the R-input of the RS flip-flop and the output of the HE element, whose input is the synchronous input of the block, the S-input of the KZgt trigger, is the input of the mode of the block The D-inputs of the DV-register are the information inputs of the block, the difference is which is connected to the D-input of the DV-trigger and the output of the first selector, the third inputs of the first and second comparison blocks are connected to the control-20 | NMY outputs, respectively, of the DV-register and DV-trigger, the fifth inputs of the first and second comparison blocks are combined and are the reset input of the memory block, the output of the first block so that, in order to improve the reliability, 25 comparisons are connected to the inputs of the selectability of the memory unit, the first and second selectors, and the first and second secondary inputs of the failure analysis unit are entered into it, the information input of which is connected to the output of the second block, the comparers, the first and second blocks of the comparison, the failure analysis block and the DV trigger, the D input of which is connected to the first input of the second comparison block and the output of the first selector, whose information inputs are connected to the first inputs of the first the comparison unit, with the corresponding information3Q, the output of the second selector is the information output of the memory block, the first and second outputs of the failure analysis block are the outputs of the failure and partial failure of the block memory. which is connected to the D-input of the DV-trigger and the output of the first selector, the third inputs of the first and second comparison blocks are connected to the control-20 | NMY outputs, respectively, of the DV-register and DV-trigger, the fifth inputs of the first and second comparison blocks are combined and are the reset input of the memory block, the output of the first block 3Q, the output of the second selector is the information output of the memory block, the first and second outputs of the failure analysis block are respectively the outputs of the failure and partial failure of the memory block.