SU1525678A1 - Microprocessing system for program control of processing equipment - Google Patents

Abstract

The invention relates to microprocessor technology and can be used in automated systems for programmed control of technological processes, for example, in systems of numerical programmed control of industrial complexes, robotic manipulators, etc. The aim of the invention is to improve the performance of the microprocessor system by introducing an adaptive data sampling mode. A microprocessor system for software control of process equipment consists of a microprocessor, a clock generator, an address buffer system controller, a memory address decoder, a fixed memory, RAM, an RAM driver, an input / output address decoder, input device bus drivers / output, first and second elements AND, three elements OR. 2 Il.

Description

The invention relates to microprocessor technology and can be used in automated systems for software control.

technological processes, for example, in systems of numerical program control of industrial complexes, robotic manipulators, etc.

The purpose of the invention is the performance of a microprocessor system by introducing an adaptive data sampling mode.

FIG. 1 shows a functional diagram of a microprocessor system; in fig. 2 - time diagram of the microprocessor system in the adaptive data selection mode,

The microprocessor system for software control of technological equipment contains a processor 1 with address outputs 1 I, data inputs and outputs 1.2, output 1 and 3 control clock inputs 1.4 and 1.5 of the first and second phases input 1.6 reset, input 1.7 readiness and output 1.8 synchronization 5 clock generator 2. with inputs 2.1 and 2.2 for connecting a quartz resonator, input 2.3 for synchronization, clock outputs 2.4 and 2.5 for the first and second phases, output 2 for reset by output 2–7 ready and output 2–8 synchronization The system controller 3 with the outputs-inputs 3.3 of the data j is the microprocessor-based data bus of the system and the outputs of control 3.2; Owned by Goschki1 AL by control bus: microprocessor system, 4 cres buffer with outputs 4, 1 s are your microprocessor sion ™ tag-id decoder 5 memory addresses with output 5.1 of connecting permanent memory and output 5.2 of connection operative pag-etti, constant memory b, operative memory 7, memory processor 8, decoder 9 addresses of input / output devices with codes 9.1 of the I / O device utilization and output 9 -. 2- 9.4s bus driver 10 input-output devices 5 first 11 and second 12 elements OR, decoder

13 permanent data memory ,,, first

14 and a second 15 persistent data memory g first 16 and second 17 triggers, counter 18, register 19s first

20 and second 21 elements AND 5, third element OR 22; input 23, which is a microprocessor-based reset input, input 24, which is a ready input to a microprocessor system 5, input 25, which is a capture input from a microprocessor system, input 26, which is an input to an interrupt / microprocessor system request, output 27, which is an output standby CRS system, VEKOD 28, is the output of the interrupt enable resolution of the 1 microprocessor system inputs 9, which are the information inputs of the microprocessor system, and the outputs 30, which are information courses of the microprocessor Seme,

Perv 2.1 and 2.2 second inputs of the clock generator connected to a quartz resonator. The input 2.3 of the clock generator 2 is connected to the synchronization output 1.8 of the microprocessor 1. Pervyi 2.4 and the second 2.5 outputs of the clock generator 2 are undercaped to the first 1 1 4 and the second 1.5 clock inputs of the gzhc-processor 1, respectively. 2 „6 and fourth 2.7 outputs of the clock generator, 2 slots to the reset inputs 1, 6 and readiness 1.7 of the coprocessor 1, respectively; Fifth output 2.8 of the clock generator 2 is connected to the clock input of the sys- tem controller: 3, Address output 1, , f iKponDO- cc of the subcategory to information on the inputs of buffer 4 a resgi Vhody- outputs 2 data. Shakroprocessor 1 is connected to the inputs ETEggsody data of the system KOHTpojixiepa Zo Control outputs 1 and 3 g-processor 1 are connected to the control inputs of the system controller 3 "First and second inputs of the resolution of buffer 4, address of the bus 3 (very much ra Bcprocessor system Supports, Capture, Information More than the inputs of the decoders 5 and 9 of the memory address .I addresses of the I / O devices are connected to bus 4 from 1 address of the processor system The resolution of the decoder 5 a. Memory address is connected to the output of the first element RTffi nepBbtti and the second inputs of which are connected to the ESCHNY 3.2 discharge. Microprocessor system diagnostics2 Reading the memory, Closed in memory, respectively First output of the decoder 5 of the naiviHTi i address is connected to the nepjBOMy constant-resolution enable input, U1. 5.2 of the memory address decoder 5 is connected to the enable input of the operational 7 and to the first enable input of the bus driver RAM. The second resolution enable input of the 6th memory is connected to the bit

microprocessor control outputs 1.3 1.3 Received, also connected to the second enable input of the bus driver 8 RAM. Record entry memory 7 is connected to the discharge bus 3.2 control microprocessor system Record in memory. The address inputs of the constant 6 and operational memory 7 are connected to the bus 4.1 of the microprocessor system address. The information outputs of the fixed memory 6, the inputs-outputs of the bus drivers 8 and 10 of the RAM of the I / O devices are connected to the data bus 3.1 of the microprocessor system. The outputs of the tire driver 8 of the memory are connected to the data inputs of the RAM 7, the data outputs of which are connected to the inputs of the bus driver of the memory 8. The enable input of the decoder 9 addresses of input / output devices is connected to the output of the second element OR 12, the first and second inputs of which are connected to microprocessor system control bus 3.2 bits. Input from input device, Output to output device, respectively. The group of information outputs 9.1 of the address decoder of I / O devices 9 is connected to the first resolution inputs of the corresponding bus drivers 10 I / O devices, the second resolution inputs of which are connected to the microprocessor system control bus 3.2 input from the input device. The outputs of the bus I / O drivers 10 are the information outputs 30 of the microprocessor system, and their inputs are the information inputs 29 of the microprocessor system. The information inputs of the data memory decoder 13 are connected to the bus 4.1 of the microprocessor system address, and its enable input is connected to the microprocessor system control bus 3.2 read memory. The output of the decoder 13 constant data memory is connected to the first inputs of the first 20 and second 21 elements I. The second output 9.2 of the decoder address of the I / O devices is connected to the input of the first trigger 16. The third output 9.3 of the decoder address of the I / O devices is connected to the first the input of the third element OR 22, the second input of which is connected to the third r - output 2.6 of the clock generator 2. The fourth 9.4 output of the address address decoder memory 9 is connected to the input of the second trigger setup 17. The output of the third element OR 22 is connected to the input resetting the first 16 and second 17 flip-flops, counter 18 and the register 19. The output of the first flip-flop 16 is connected to the second inputs of the first 20 and second 21 elements I. -triggera second output 17 is connected to the input of the synchronization register 19,

The output of the first element AND 20 is connected to the first resolution input of the first permanent memory 14 of the data, the second resolution input of which is connected to the microprocessor system control bus section 3.2 Reading the memory connected also to the second resolution input of the second permanent memory 15 of data. The output of the second element And 21 connected to the first input

enabling the second permanent memory 15 of the data, as well as to the midpoint 1gt input of the counter 18. The outputs of the counter 18 are connected to the first part of the address inputs of the second permanent memory I5 of the data, the second part of which is connected to the outputs of the register 9. The outputs of the first 14 and second 15 The fixed data memory, as well as the inputs of register 19, are connected to the data bus 3.1 of the microprocessor system. The address inputs of the first permanent memory 14 of the data are connected to the address bus 4.1 of the microprocessor system.

The microprocessor system for the programs of the new control of technological equipment operates as follows.

Normal mode of operation.

In this mode, the clock generator

2 (Fig. 1) forges two non-overlapping clock sequences, which from its 2.4 and 2.5 outputs go to the clock inputs of the first 1.4 and second 1.5 phases of the microprocessor 1,

The stability of the clock frequency is ensured by a quartz resonator connected to the inputs 2.1 and 2.2 of the clock generator 2.

The microprocessor 1 generates the address, data and control signals after applying a reset signal to its corresponding input 1.6, and the external reset signal from the input 23 of the microprocessor system 1 is gated to

act generator 2 and enters its code 2,6, after setting level 1 at input 24 of the microprocessor system, and the ready signal is gated in the clock 2 and from its output

2.7 arrives at the microprocessor 1 ready input 1 7, If the signal O is set at the input 24 of the microprocessor system, then the output 1 of the microprocessor system 27 sets the signal 1, indicating

that microprocessor 1 is in idle mode.

The microprocessor 1 outputs the word sos on the bus 1 „2 data, on the sync signal at the corresponding output 1.8, coming to the input 2.3 of the clock generator 2 in the first cycle of each machine cycle, and the strobe signal in the first phase synchronization (system strobe) from the exit

2.8-cycle generator 2 is fed to the system sync input

controller 3, in which the microprocessor status word is written from the data output 1.2 of the processor / processor 1 1.2. System: counter.p. 3 by the status word and the output signals 1.3 of the microprocessor control 1 forms the control bus 3.2 microprocessor system, as well as data buses 3, 1 microprocessor system, ensuring it requires 5y load capacity and bi-directionality of data transmission at the inputs-outputs 1.2 data microprocessor 1,

Buffer 4 addresses forms by address signals on the corresponding outputs 1.1 of the microprocessor 1 bus 4.1 addresses of the microprocessor systeg system providing it. required load capacity "

The microprocessor system can be switched to the interrupt and capture mode by supplying the corresponding signals to inputs 25 and 26. When switching to the interrupt mode from output 28, the interrupt enable signal is removed. When the microprocessor system goes to the capture mode, the corresponding output of control outputs 1 .3 the microprocessor 1, as well as on the microprocessor system control bus 3.2, sets the capture confirmation signal, which transfers the outputs of the address 4 buffer to the high-impedance one via the first and second control inputs

condition. By this signal, the outputs of ciicTeNffloro of controller 3, outputs 1.1 of addresses, inputs-outputs 1.2 of data of microprocessor 1 are transferred to the high-impedance state. Cutting and interruption in the proposed microprocessor system are not used.

The microprocessor 1 reads and executes the program recorded in the permanent memory 6 or in the RAM 7. In this case, the decoder 5 of the memory address decrypts the address set on the bus 4.1 of the address of the microprocessor system if one of the signals Read, Write to the memory, activates the output of the first element OR 11 and the control input of the decoder 5, If the constant memory address 6 is set on the bus 4.1 of the microprocessor system address, the output 5.1 of the decoder 5 and the first control input are activated cost of paired- 6,

If the address of the memory 7 is set on the address bus 4.1 of the microprocessor system, then the output 5o2 of the decoder 3, activates the memory control input 7 and

the first control input of the drive memory driver 8.

Outputs of the fixed memory B are connected to the 1F data bus of the Kroprocess - weed system, if the j-switch of the first control input is activated, the second signal control input When it comes to the corresponding bit of the output-. Microprocessor control terminal 1, 1.3, Data is read from cells of the fixed memory b into microprocessor 1 via bus 3'2 data of the g-processor system via the input-output data inputs of the system controller to the inputs-outputs K 2 data of the front-end processor 1 in

according to the addresses coming to the address inputs from the bus 4.1 addresses of the microprocessor system.

To read data from RAM 7, in addition to activating its control input, an O signal is sent to its write input from the corresponding microprocessor control bus 3.2; Record B is a memory, and the second control input of the bus driver 8 is activated by the output of the microprocessor 1 control outputs 1.3 Reception. This translates the tire form -

The memory .8 memory in receive mode, i.e. data is transmitted from the outputs of the RAM 7 to the bus 3.1 of the microprocessor system data. The data is read from the memory cells 7 into microprocessor 1 via bus 3.1 of the microprocessor system data in accordance with the addresses, received at its address inputs from bus 4.1 of the microprocessor system.

The teiKponpoueccop 1 can write data to the RAM 7, with this bus driver 8 operating memory on the second control input, from which the active level is removed from the corresponding output of the microprocessor 1 control outputs 1.3, is transferred to the data input mode from the data bus 3.1 microprocessor system.

The operational memory 7 is connected to the recording input, which is activated by the corresponding bit. The recording in the memory of the microprocessor control box 3.2 is transferred to the recording mode. Data from the 3.1 data bus of the microprocessor system is recorded in the RAM 7 cells in accordance with the address signals received at the address inputs from the 4.1 bus address of the microprocessor system In the absence of active levels of control signals, the outputs of the fixed memory 6 and the bus-output outputs the memory driver 8 is in a high-powered state and disconnected from the bus 3.1 of the microprocessor system data.

The microprocessor system enters data from its information inputs 29 or outputs data to its information outputs 30. The decoder 9 addresses the I / O devices decodes the address, set on the bus 4.1, the addresses of the microprocessor system, if its input is activated to control the output of the second element OR 12 at activating its inputs from the signals input from the input device, output to the output device on the corresponding bits of the microprocessor control system bus 3.2. The outputs of the decoder 9 control input-in addresses The outputs activate the second input of the resolution of one of the bus I / O drivers corresponding to the address that I input to the a, and the local inputs of the desinator 9 to the address of the I / O devices.

Mode of operation (input or output) tires. I / O device drivers are determined by the signal at the second resolution inputs, i.e. by resynchronization Enter from. input devices bus 32 control microprocessor system. In the input mode, data from the information inputs 29 of the microprocessor system is fed to the inputs of the corresponding bus driver of the I / O device and from its inputs and outputs to the bus 3.1 of the system microprocessors data through the system controller 3 to the skin processor I through its data inputs-outputs,

In the output mode, data from the MiKpo processor 1 on the inputs-inputs to the 1.2 data, through the system controller 3, on the 3.1 axis of the microprocessor system data is fed to the input-outputs of the corresponding bus driver of the I / O device, and from its outputs - to the information inputs microprocessor system.

With OTcyTCTBiiH active levels of control signals, the bus drivers of the I / O device are disconnected from the data bus (are in a high impedance state).

The microprocessor system implements an algorithm for modeling a programmable logic array that is standard for calculating systems of Boolean functions describing the law of control of technological equipment. Such an algorithm is designed as a PLA procedure in a high level language for PL / M microprocessors. At the same time, the input state vector of the process equipment is input from the input port (s), and the output vector of control signals is output to the output port (s) in the same way as described.

Conjunctive term processing

Boolean functions consist in calculating the values of each term, regardless of their values, on different sets of input vectors.

Realization mode; and adaptive data sampling.

In this mode, the microprocessor-based system operates in the same way as usual, and executes a program for simulating a programmable logic | Matrix. Having found that the conjunctive | ny term of the system of Boolean functions, which describe the law of control of technological equipment, is 11, the microprocessor 1 executes the output command at the trigger address 16. At the same time, the output information, i.e. the contents of the battery is not significant, it is important that the output 9.2-decoder 9 addresses the I / O devices is excited. Therefore, a trigger 17 is set, reset to zero at the start of a system reset operation. The output of the trigger 16 (inverse) is set to the voltage O, so the second input element And 20 is blocked, and the element And 21 is prepared for operation. Next, the microprocessor 1 displays at the address of the trigger 17 address of the next conjunctive term. At the same time, output 9.4 of the decoder 9 addresses the I / O devices is activated and a second trigger 17 is set, reset to zero by a system reset from the output of the third element OR 22. As a consequence, the register 19 is connected via information inputs from the 3L bus. data of the microprocessor system, the leading edge of the signal at the output of the second trigger 17 is recorded as the ad i pec of the next conjunctive term I „

I Since the first one is installed, the trigger 16 AND is blocked at the second input element AND 20, the permanent memory I 14 is disconnected from the data bus, i.e. Its outputs are translated into a high-imperative state. Next, the Microprocess: weed system continues to implement a program for modeling a programmable logic array, which with the exception of the commands for outputting the address of trigger 16 and outputting the address of the next conjunctive term at the address of register 19 and resetting, if the next calculated conjunctive term is 1, corresponds to the standard. The microprocessor sets on the bus 4.1 the address of the next data memory location, i.e. next conjunctive term, thus activating the output of the decoder 13 permanent data memory. However, since the trigger 16 is set, the first resolution input of the first constant data port 14 is not activated, but the first resolution input of the second constant

data memory 15, the second resolution input of which is activated by the corresponding read signal of the control bus memory. In the second permanent memory 15 data at the address set on the outputs of the counter 18 and the register 19j recorded data on conjunctive terms, not orthogonal calculated. The change in the state of the counter 18 occurs on the falling edge of the signal at the output of the decoder 13. Consequently, after detecting a single conjunctive term, the data is sampled from the second permanent memory 15 data to the addresses formed by the counter 18 with the offset provided by the register 19. In this case, the microprocessor the system processes a subset of data of lower power, namely a subset of conjunctive terms that are not orthogonal to the computed first unit. When a new unit term is found in this subset, the microprocessor system processes the same subset of data, since the first 16 and second 17 triggers are already installed and the next output commands to their addresses do not change, their states.

Data processing ends when a completion mark is detected, which completes each and the subsets of data recorded in the second permanent memory 15. Resetting the first 16 and second 17 triggers, register 19 and counter 18 is reset by the output command when the output 9.3 of the decoder 9 is excited. I / O devices.

In the event that none of the conjunctive terms equals 1, the microprocessor system continues to process the data located in the first permanent memory 14 of the data until it detects the end of computation marker, which completes the full array of data.

Thus, the average processing time of an array of data encoding conjunctive terms of a Boolean function system, describing the law of control of technological equipment, on the flow of input state vectors of technological equipment is reduced.

Consider an example of a specific implementation of a processor system for software control of process equipment that implements the control law, which is described by the following system of Boolean functions:

, x „uhzH2,; 5

Zi X3X, vx3X2 /X3X2X,vx,,XoVXjX.,x,Xo;

jZ ,, 4i3X2VX3X ,, VX3X.jX, X, VX3Xo; J X XiXoV / X XjVXjXoVXjX-jX X ..

By non-repeating conjunct term terms:

, Xjx,

Xjx

Xjx jx

Xjx

 ,

Xix

; Assign them serial numbers 1–11 and draw up a matrix of non-orthogonal components, taking into account the serial number, i.e. non-orthogonality is taken into account in relation only to the following terms by number:

23456789 1011 11 1

21

3II 1

4 G

5.11

61

7. 1

81 9

10 1

The matrix of non-geometricon shows which conjunctive terms need to be calculated if the term whose number corresponds to the line number is 1. The remaining terms are not subject to calculation, since they are orthogonal to this term and, accordingly, are equal to O.

In the first permanent memory 14, the data has constants D (of a value of significant bits). T, - (clearings of direct values of variables), M (values of the system of functions with conjunctive term 1 equal), where i is the number of the term (see Table 1).

T a b l and c a 1

1001

M.

15

20

25

thirty

35

40

Place the information in the second data storage 15 in accordance with the non-orthogonal matrix (Table 2).

Table 2

50

Marker

15

1525678

Continued t ab.2

INPORT 0

MOVB, A

ADA: MVIС, 0

LXIM.TABL

MOVB, A

ANAM

NEXT: INXH

XRAM

INXH

INZ CHECK

OUTPORT2

MOVA, L

OUTPORT3

MOVA, C

ORAM

MOVC, A

CHECK: INXH

Suba

ADDM

INZNEXT

MOVA, C

OUTPORT 1

OUTPORT4 RET

TABL: DB

Input Input Vector Save Input Vector Zero the result register Initialize the memory

Select significant variables Memory pointer increment O if term equals 1

Output to the address of the first trigger Address of the next term in A Output to the address of the register

Formation of output signals

Zero battery

There is a graduation marker

No, calculate the term

B A - output signal

Control signal output

Zero triggers, register, counter

Return

Masks describing conjunctive terms

Continuation of table 2

Consequently, with the exception of four commands OUTPORT 2, MOVA, L, OUT PORT 3,4 program corresponds to the known ..

Thus, the microprocessor system reduces the time spent on calculating the law of control of technological equipment specified by the system of Boolean functions by more than 1.6 times.

Claims (1)

Invention Formula Microprocessor system for software control of technological equipment, comprising a microprocessor, a clock generator, a system controller, an address buffer, a memory address decoder, a post-low memory, a RAM, a bus RAM driver, an I / O device address bus, bus shapers of input-output devices5 are the first and second elements OR5 and the first and second inputs of the clock generator are connected to a quartz resonator, the third and fourth inputs of the clock generator are in Tc reset and readiness inputs of the microprocessor system, respectively; 5 clock input of the clock generator: connected to the sync output of the microprocessor, the first and second clock generator outputs are connected to the first and second clock inputs of the microprocessor, respectively, the third and fourth outputs of the clock generator are connected to the reset inputs and the availability of the microprocessor, respectively, the fifth and sixth inputs of the microprocessor are the inputs for capturing and interrupting the request of the microprocessor system, respectively, the first and the second outputs of the microprocessor are provided by the waiting and resolving outputs of the microprocessor system, respectively, the five clock output is connected to the synchronization input of the system controller, the microprocessor address outputs are connected to the information buffer address inputs, the microprocessor data inputs and outputs are connected to the data input outputs the system controller, the microprocessor control outputs are connected to the control inputs of the system: the dark controller, the data output outputs of the system controller in The microprocessor system data bus, the system controller control outputs are the microprocessor system control bus, the first and second addresses of the address buffer enable are connected to the microprocessor system control bus, the capture acknowledgment, the address buffer outputs are the address bus of the microprocessor system, the information decoder addresses of the address the memory and addresses of I / O devices are connected to the address bus of the microprocessor system, the enable address of the memory address decoder is connected to the output of the first element OR, the first and second inputs of which are connected to the microprocessor system control bus bits Read memory, Write to memory, respectively, the first output of the memory address decoder is connected to the first permanent memory enable input, the second output of the memory address depshfrarator connected to the memory enable input and the first bus enable input of the operational memory; the second memory enable input is connected to the microprocessor control outputs; and Connected to the second permission input of the bus RAM driver, the RAM recording input is connected to the microprocessor system control bus. Record in the memory, the fixed and RAM memory address inputs are connected to the microprocessor system address bus, the information outputs are permanent. memory, inputs / outputs of bus drivers for RAM and I / O devices are connected to the data bus of the microprocessor system; Outputs of the RAM driver for memory are connected to inputs data memory, the data outputs of which are connected to the inputs of the bus memory driver, the enable input of the I / O device address decoder is connected to the output of the second SHSh element, the first and second inputs of which are connected to the microprocessor control bus bits. Input from the input device, Output to the output device, respectively, a group of information outputs of the device address decoder (I / O is connected to the first resolutions of the corresponding (pin I / O drivers, the second permission inputs are connected to the microprocessor system control bus discharge. The input from the input device, the I / O bus driver outputs are information outputs of the microprocessor systems, and their inputs are information inputs of the microprocessor system, which, in order to improve the performance of the microprocessor system, additionally contains a read-only memory decoder data, the first and second permanent data memories, the first and second triggers, the counter, the register, the first and second elements AND, and the third element OR, and the information inputs of the constant memory decoder and address decoder are connected to the address / output bus of the microprocessor system, the resolution of the decryptor of the permanent data memory is connected to the discharge Read memory of the control bus, the output of the decoder of the permanent memory is connected to the first inputs of the first and second elements AND, the second output of the address decoder y troystv input-output connected to the set input of the first flip-flop, the third output of the decoder input device addresses | OUT connected to the first input of the three 50 five the second OR element, the second input of which is connected to the third output of the clock generator, the fourth output of the memory address decoder is connected to the installation input of the second trigger, the output of the third OR element is connected to the reset inputs of the first and second triggers, the counter and the register, the output of the first trigger is connected to the second the inputs of the first and second elements AND, the output of the second trigger is connected to the register synchronization input, the output of the first element AND is connected to the first resolution input of the first permanent data memory, the second input is The resolution of which is connected to the microprocessor system control bus section. Reading the memory, which is also connected to the second permission input of the second permanent data memory, the output of the second And element, is connected to the first enable input of the second permanent data memory, as well as to the counter input of the counter , the counter outputs are connected to the first group of address inputs of the second permanent data memory, the second group of which is connected to the register outputs, the outputs of the first and second permanent data memory, and also the register inputs are connected to w no data microprocessor system, and the address inputs per- 1VOY constant data memory podklyuche- us to the address bus of the microprocessor system. NTS crt SP SS "about Yu Ui