SU1515294A1 - A.c. to d.c. voltage converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used to power low-voltage integrated circuits, such as injection logic devices. The purpose of the invention is to increase efficiency and ensure operability at low input voltages. In the converter, at a positive half-wave of the input voltage, capacitor 8 is charged through a MIS transistor 1 with an induced P-channel, forced open by a negative voltage on the capacitor 7. At a negative half-wave of the input voltage, the capacitor 7 is charged through a MIS transistor 2 with induced N -channel forced open by a positive voltage across the capacitor 8. The output voltage of the converter is the sum of the voltages on the two capacitors 7 and 8, each of which even at small values it is equal to the input voltage. 1 il.

Description

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The invention relates to electrical engineering and can be used to power low-voltage integrated circuits, such as injection logic devices.

The purpose of the invention is to improve efficiency and ensure operation at low input voltages.

The drawing shows an electrical circuit for converting an alternating voltage into a constant voltage.

The converter consists of a MDS transistor 1 with an induced p-channel, the source of which is connected to the source of a MOS transistor 2 with an induced p-channel and a gate of the MOS transistor 3 with an induced p-channel and an MIS transistor A with an induced p-channel - cash. The gate of the MOS transistor 2 and the drain of the MOS transistor 4 are connected and connected to the cathode of diode 5, the anode of which is connected to the cathode of diode 6 and the second plates of capacitors 7 and 8, as well as to the second input terminal 9. The first plate of the capacitor 7 is connected to the gate of the TIR the transistor 1, the drain of the MD1 transistor 3 and the second output terminal 10. The first plate of the capacitor 8 is connected to the substrate and the source of the MOS transistor 4, the drain and the substrate of the MOS transistor 1 and the first output terminal 11 of the first input terminal 12 is connected to the source MOSFET 1. Load -screw resistor 13 is connected to the output terminals 10 and 11.

The device works as follows.

At a positive input-voltage half-wave and g, capacitor 8 is charged through an open MOS transistor 1, and at a negative II g half-wave capacitor 7 is charged through an open MOS transistor 2. At a positive half-wave U

MOS transistor 3. and the negative voltage from the capacitor 7 is fed to the gate of the MOS transistor 1, forcing it to open. Since in this case the channel resistance of the MIS transistor 1 becomes extremely small, the capacitor 8 is charged almost to the value of U g (the loss of the circuit is minimal). With a negative half-wave U, the MOS transistor 4 opens and a positive voltage from the capacitor 8 is supplied to the gate of the MIS transistor 2,

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Forcing it to open “Since in this case the resistance of the channel of the MIS transistor 2 becomes extremely small, the capacitor 7 is charged almost to the magnitude, (the losses of the circuit are minimal). The load resistor 13 is turned on in such a way that it is affected by the total voltage across the capacitors 7 and 8, i.e., the output voltage and 5y 2 and i Diodes 5 and 6 are turned on for overvoltage MOS transistors 2 and 1

In the device, capacitors 7 and B have a double function: firstly, they force the output voltage and, secondly, they provide a forced charge of each other with minimal losses. Thus, the voltage on the capacitor 7 helps to reduce the loss resistance in the MIS transistor 1 when charging the capacitor 8, and the voltage on the capacitor 8 helps to reduce the loss resistance in the MIS transistor 2 when charging the capacitor 7. Such a positive This leads to the achievement of the goal set in the invention. The output voltage is equal to 2 and 5 g, even with a small input voltage. The device has an increased efficiency when operating at low voltages. For efficient operation of the converter, it is desirable to use MIS

transistors with low threshold voltages. In addition to capacitors 7 and 8, the device is simply implemented as a monolithic integrated circuit.

Claims (1)

Invention Formula A variable-voltage-constant-voltage converter containing a main MOS transistor with an induced p-channel, the source of which is connected to the source of the first MOS transistor with an induced p-channel, the gate of the second MOS transistor with an induced p-channel, and the first input transistor, the drain of the main MOS transistor is connected to the first output transistor, and the gate is connected to the drain of the second MOS transistor with an induced p-channel, and the source and substrate of the second MOS transistor with an induced p-channel are connected to the drain and odlozhkoy first MIS transistor and the first plate of the main capacitor of m and n 515152946 due to the fact that, with the aim of a MDP transistor with induced efficiency and ensure the operation of the p-channel and the cathode of the first imposition at small input eg the diode, the anode of which is connected to a capacitor, two second input pins, a second obdiode, and an additional MIS trans-clutch for both of the indicated p-channel capacitors, springs, and the cathode of the second input diode and whose substrate is connected, the anode of which is connected to the main flow conduit transistor of the main MOS transistor with an induced p-channel and the first jg dual of the p-channel, and the input capacitor of the injected capacitor, the current of the second MOS transistor with an inductor connected to the first input of the p-channel om connected to at the output, and the drain - to the gate of the first output output