SU1513406A2 - Device for automatic measuring of amplitude of variable signal - Google Patents

Abstract

The invention relates to the field of measurement technology, namely, devices for automatically measuring the amplitude of a variable signal. The aim of the invention is to improve the accuracy of measurements when expanding the dynamic range. The device contains serially connected frequency converter 1, switch 2, intermediate frequency amplifier 3, quadratic detector 4, modulation frequency amplifier 5, phase detector 6 and zero indicator 7, series 8 reference signal generator, amplifier 9 and attenuator 10, key 11, generator 12 switching frequency, formers 13, 14, the counter 15 and the threshold unit 16. 1 Il.

Description

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The invention relates to the field of measurement technology, namely, devices for automatically measuring the amplitude of a variable signal, and is an improvement on the device according to the author. IP 711482.

The aim of the invention is to improve the accuracy of automatic measurement while expanding its dynamic range.

The drawing shows a device for automatically measuring the amplitude of a variable signal.

The device contains serially connected frequency converter 1, switch 2, intermediate frequency amplifier 3, quadratic detector 4, frequency modular amplifier 1 THF5 amplifier 5 phase detector 6 and 7 zero indicator 5 serially connected reference signal generator 8, reference signal amplifier 9 and attenuator 10, key P, switching frequency generator 12, discriminator 13, driver 14 clock pulses, reversible counter 15 and threshold unit 16. The output of attenuator 10 is connected to one of the inputs of switch 2 connected to each other their input; via key 11 with one of the generator outputs 12 of the switching frequency. The latter is also connected by other outputs to one of the inputs of the phase detector 6, to the first input of the formazater-discriminator 13 and to the first input of the driver 14 sync pulses. The second input of the driver 14 of the clock pulses is connected to the first input of the reversible counter 15 connected to the first output of the driver — the differences are bodies 13. The third input of the driver 14 of the clock pulses is connected to the second input of the reversible counter 15 connected to the second output of the drivers 14, the receiver 13. One of the outputs of the amplifier 5 modulation frequency through the threshold unit 16 is connected to one of the inputs of the discriminator Shaper 1 The first 1 of the outputs of the reversible O counter 15 is connected to the attenuator 10,

The device contains the first 17, second 18, third 19 and quarter 20 logical elements AND, logical element OR 21, first information key 22, decrypted 23, 24 clock pulse generator, inverter 25, counter 26

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Yes, the divider 27 and the averaging counter 28 connected in series, the second information key 29 and the indicator 30, the group of inputs of the second information key 29 are also connected to the second group of reverse codes counter 15 and to the group of inputs of the first information key 22. The group of outputs of the first information key 22 is connected to the counter 26 of the return code, the output of which through the decoder 23 is connected to the first input of the first logical element AND 17, which is connected to the first input of the second lot of the logical element And 18. To the second input The first logical input element AND 17 is connected to the first input of the third logical element AND 19 and the first output of the divider 27, the second input connected to the first control input of the averaging counter 28. The third input of the first logic element And 17 is connected to the generator of 24 clock pulses. The fourth input of the first logic element AND 17 is connected to the output of the inverter 25 and to the input of the divider 27. The input of the inverter 25 is connected to the control input of the first key 22 of the information, with the output of the driver 14 clock pulses and 20 connected to the output of the first input of the logical element OR 21 "The fourth logical element AND 20 is connected with the second control input to the first control input of the second information key 29 and one of the outputs of the second group of spinner counter 15 codes. Additional code reversible counter 15 is connected with the second input of the second logical element AND 18, with the second input of the third logical element and with the output bus 31. The second logical element And 18 is connected with the counter 26 of the return code, and the third logical element And 19 is connected by the output to the second control the second input of the second information key 29 and the second input of the logic element OR 21. The output of the latter and the group of outputs of the second information key 29 are connected to other output buses 32 and are the recording outputs of the device da1 automatic from Eren AC signal amplitudes.

The device also includes a sequential memory block 33, a comparison block 34, a buffer memory block 35 and a subtraction block 36, through which the second logic element And 18 is connected to the averaging counter 28, the delay block 37, the serial comparison element 38 and counter 39 inversions. The second logic element AND 18 is also connected to the inputs of the buffer memory unit 35 and the sequential comparison element 38 and to the input of the delay unit 37 connected by an output to the input of the subtraction unit 36. The output of the serial comparison element 38 is connected to the input of the inversion counter 39 connected by an output with the input of the comparison unit 34. The inputs of the frequency converter are connected to the outputs

At a sufficiently high pitch signal of the information counter 15, Vt is fed to the indicator 30 of the bus 32, from which it goes to the information input of the recording devices. synchronization of external reg devices from a logical OR 21 through one of the output

block 40 playback.

The DD1Y device automatically emits sync pulses, the measurement of the amplitude of the variable signal works as follows.

The measured signal reproduced from the magnetic recording medium in reproduction block 40 passes 25 through a frequency converter 1 to a switch 2 acting on the intermediate frequency amplifier 3. Switch 2 also receives a return

In the case of reducing the generated signal below the readings, the reversible 15 generates a pulse, after the second and third logically, And 18 and 19. At the same time, the informative counter 15 does not pass the second key 29 of the informer 30 and doesn’t pass through the clock sync pulses m logical element gic element Iuy1 21. i

a signal passing through the amplifier 9 30 of the reference signal and an attenuator 10 from the generator 8 of the reference signal. Switch 2 switches with the frequency of the signal fed to it through

: generator 12 frequency com- At the same time, it is provided that something is measured, then reference

key 11 mutations. exclusion

signal to the amplifier 3 intermediate frequency, acting through a quadratic detector 4 to the amplifier 5 modulation frequency. In case of equality of amplitudes, the switched signals from the amplifier 5 of the frequency modulation signal is not supplied. In case of a change in the amplitude of the measured signal relative to the reference signal from the amplifier 5, the frequency modulation signal is supplied. If the error signal exceeds the trigger level of the threshold block. 16, it produces a signal to the driver-discriminator 13, which determines the direction of misalignment of the switched signals. Depending on which of the commutation-dominated signals prevails, the former forms 13 generates a signal acting on the first or second inputs of the reversible counter 15,

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the state of which determines the degree of attenuation introduced by the attenuator 10 into the reference signal. In this case, the state of the reversible counter 15, corresponding to the equality of the switched signals, reflects the relative value of the measured signal.

At a sufficiently high level of the measured signal, information from the reversible counter 15 through the second key 29 is supplied to the indicator 30 and to the output buses 32, from which it is fed to the information inputs of external recording devices. To the synchronization inputs of external recording devices from the logical element OR 21 through one of the output buses 32

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In the case of a decrease in the magnitude of the measured signal below the level of unstable readings, the reversible counter 15 generates a pulse arriving at the second and third logic elements 18 and 19. At the same time, the information of the reversible counter 15 does not pass through the second information key 29 to the indicator 30 and to the output tires 32 and the sync pulses from the shaper 14 sync pulses do not pass through the fourth logical element I 20 to the logical element Iuy1 21. i

Each sync pulse from the sync pulse generator 14 via the first information key 22 ensures that the state of the reversible counter 15 is transferred to the counter code 26. At the end of each clock pulse, the first logic element I G / passes from the generator 24 clock pulses clock pulses, the number of which determines the number of samples. Samples are passed through the second logical element AND 18 to the buffer memory block 33, to the inversion counter 39, to the sequential comparison element 38 and to the RAM block 33, which calculates the average value of the inversions of these samples. The RAM unit 33 operates on the comparison unit 34 directly, and the sequential comparison element 38 via the inversion counter 39. Block 34 compares by comparing inversions from the memory block and from inversion counter 39 and outputs a noise component to the control unit 36 through the buffer memory block 35, which is affected by the signal-to-noise mixture affecting a subtraction unit 36 also via an inversion counter. Cleared from noise, the counts from the subtraction unit 36 are fed to the average counter 28. When the reverse code counter 26 overflows, the decoder 23 stops the receipt of clock pulses from the 24 clock pulse generator through the first logic element AND 17. At the same time, the averaging counter 28 records the number of pulses corresponding to the state of the reversing counter 15. The appearance of each next sync pulse results to repeat the described sequence of operations. Upon arrival from the divider 27 of the rewrite pulse, information from the averaging counter 28 is transferred via the second information key 29 to the indicator 30 and to the output buses 32.

Formula and 3 about 11

A device for automatic measurement of the amplitude of a variable signal according to the author's code No. 711482, which is because, in order to improve the accuracy of the automatic measurement while expanding its dynamic range, a series of operational memory a comparison block, a buffer memory block and a subtractor through which the second logic element I is connected, with an averaging counter, a delay unit, a series comparison element and an inversion counter, the second logic element AND connected to the input m of the buffer memory block and the serial comparison element and to the input of the delay unit connected by the output to the input of the subtraction unit, and the output of the serial comparison element is connected to the input of the inversion counter, connected by the output to the input of the comparison unit.

Claims (1)

SUMMARY OF THE INVENTION A device for automatically measuring the amplitude of an alternating signal according to Auth., No. 711482, which is related to the fact that, in order to increase the accuracy of automatic measurement when expanding its dynamic range, a block connected in series RAM, a comparison block, a buffer memory block and a subtraction block, through which the second logical element AND is connected. with an averaging counter, a delay unit, a sequential comparison element and an inversion counter, the second logic element AND connected to the inputs of the buffer memory unit and the sequential comparison element and to the input of the delay unit connected by the output to the input of the subtraction unit, and the output of the serial comparison element connected to the input an inversion counter connected by the output to the input of the comparison unit.