SU1511842A1 - Closed stepping electric drive with self-switching and step-fractionating - Google Patents

Abstract

The invention relates to electrical engineering, in particular to a discrete electric drive. The purpose of the invention is to increase productivity by increasing speed and expanding operational capabilities. The electric drive contains a sine-cosine rotating transformer 2, a sensor signal processing unit 3 that generates a position code, analog signals, speeds and accelerations, a regulator 8 that generates a speed control law, a conjugation unit 6 that produces an analog error signal multiplied in digital-analog converters 9 and 10 to the sinusoidal and cosine signals, the frequency of which is determined by the position signal of the rotor of the engine 1. The signal from the output of the rotating transformer is subjected to the same modulation in block 3 2 after bringing it to the first quadrant in the quad selector 18. 1 Cp f-crystals, 3 Il.

Description

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.

with

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The invention relates to electrical engineering and can be used in automatic control systems and robotic complexes for controlling stepper motors (shed) with self-commutation and electrical crushing of a step using a sine-cosine position sensor, where

24

BOSD 3 contains a quadrant selector 18, the analog inputs of which are connected to the outputs of the ACS 2, the switching input of which is connected to the bus 14 of the code 1 of the quadrant, and the outputs to the analog inputs of the third 19 and fourth 20 PDAS, the digital inputs of which are connected to the outputs

The acquisition of high accuracy is positioned on ROM 15 and 17, and the outputs are from

of operation and reliability of operation is associated with the use of low-reducer and gearless stepper electric drive (SHEP) ..

FIG. 1 shows the functional 15 of which is connected to the bus of the reference scheme of a closed-loop electric power stage with crushing of pitch and self-switching; in fig. 2 is a block diagram of a variant of an interface unit (BS) for a controller (PP) based on a digital processor; 3-20, the first analog input of the EC b and the input is a block diagram of the BS variant for the RD voltage converter - the frequency H5, the output of which is connected to the input of the reversing counter 26, the output of which is the digital BFD 3.

BS 6 in the version for PP 8 based on a digital processor (FIG. 2) is connected by the corresponding inputs of a differential amplifier 21, the output of which is connected to the information input of the demodulator 22, the switching input

voltage (SHOE) 23 and the input of the ACS 2, and the output with the second analog input BS 6 and the input of the correction unit 24, the output of which is connected to

 based on a digital analog signal processor (signal processor).

The closed EEP (Fig. 1) contains the SED 1, the shaft of which is connected to the rotor of the us-cosine rotating transformer (SCWT) 2, the outputs of which are connected to the input of the block 25

It holds two devices for sampling-hragshni 27 and 28, which produce vybotki sensor signals (BOSD) 3, digital 30 and storage of analog values

40

the output output of which is connected to the second input of the adder 4, the first input of which is connected to the displacement assignment busbar 5, and the output to the digital input of BS 6 which is connected to the output of the adder 4 by digital input and data bus 7 to the PP 8, and the analog output — with the analog inputs of the first and second multiplying digital-to-analog converters (P-DAC) 9 and 10, whose outputs are connected to the inputs of the first and second pulse-width modulators (SHSh-l), respectively, 11 and 1.2, the outputs which are connected to the corresponding control inputs gpd and power amplifier 13, the switching input of which is. It is connected to the bus 14 of the P code of the quadrant, formed by the two highest weighted bits of the digital output of the BFD 3, (n-2) of the younger weight bits of which are connected directly to the address inputs of the permanent storage device (ROM) 15, - by turns connected to the digital inputs of the first CCAP 9 and through the block of 16 inverters with the address inputs of the ROM 17, the outputs connected to the digital inputs of the second CCCP 10.

signals and U for the time specified by analog switch 29, which provides alternate connection of outputs of devices 27 and 28 to input 35 of an analog-to-digital converter (ADC) 30. It is connected via bus analog interface 31 to bus 7 with which via parallel interface 31 connected hall a digital input

50

55

BS 6. The digital output of the parallel interface 31 is connected to the analog output of BS 6 via a digital-to-analog converter (D / A converter) 32.

BS 6 in the variant for PP 8 on the signal processor core (Fig. 3), in addition to the DAC 32, contains scaling amplifiers 33. The simplicity of the pairing in this case is due to the peculiarities of the processor.

Primary transducers with electric reduction of types SKT-6465 and 6460, VT71 and 100, DU50, DU70 and DUYO, DSPU-128, etc. can be used as SCVT 2.

The adder 4, the reversible counter 26, and the block 16 of inverters are executed on an IC of a K133 series, respectively, W; 3, IE5, and LN1.

corresponding to the upstream inputs of the differential amplifier 21, the output of which is connected to the information input of the demodulator 22, the switching input

which is connected to the reference bus by the first analog input EC b and the input voltage converter is frequency H5, the output of which is connected to the input of the reversible counter 26, the output of which is the digital BFD input 3.

voltage (SHOE) 23 and the input of the ACS 2, and the output with the second analog input BS 6 and the input of the correction unit 24, the output of which is connected to

holds two sampling devices, hragshnyi 27 and 28, which sample and store analog values

signals and U for the time specified by analog switch 29, which provides alternate connection of the outputs of devices 27 and 28 to the input of an analog-to-digital converter (ADC) 30. It is connected via bus analog interface 31 to data bus 7, with which through a parallel interface 31 connected hall a digital input

40

.

0

five

BS 6. The digital output of the parallel interface 31 is connected to the analog output of BS 6 via a digital-to-analog converter (D / A converter) 32.

BS 6 in the variant for PP 8 on the signal processor core (Fig. 3), in addition to the DAC 32, contains scaling amplifiers 33. The simplicity of the pairing in this case is due to the peculiarities of the processor.

Primary transducers with electric reduction of types SKT-6465 and 6460, VT71 and 100, DU50, DU70 and DUYO, DSPU-128, etc. can be used as SCVT 2.

The adder 4, the reversible counter 26, and the block 16 of inverters are executed on an IC of a K133 series, respectively, W; 3, IE5, and LN1.

PP 8 can be implemented on the basis of an LSI digital processor of the KP580IK80A type or a signal processor of the KM1813BE type. Depending on the type of processor, two variants of BS 6 are possible (Fig. 2 and G). The KPI100CK2 ICs are used as the 27 and 28 sampling snaps. Analog switch 29 is executed on IC K590KN. A / D converter 30 is implemented on LSI K572PVZ or LSI K572PV1, on which DAC 32 can be executed. As a parallel interface 3, BIS KR580IK55 is used. The BIS K572PV1 or K427PA is used as the PTsAP 9, 10, 19 and 20.

PWM 11 and 12, quadrant selector 18, differential amplifier 21, scaling amplifiers 33 and correction block 24, containing typical correction links necessary to obtain the desired dynamic properties of BFD 3, are performed using well-known I1AS-based K140 or KI53 amplifiers, analogue switches K590KN and comparators K521SA.

As a ROM 15 and 17, BIS K505REZ is used with sinus firmware within the quadrant 0078, 0051 and 005 or 0068-0071, which allows to obtain the information capacity of the output code from 10 to 12 bits, respectively. The demodulator 22 is implemented on an IN5 K525PS or K525PS2, and the LIS K K 108P is used as the converter 25.

The drive works as follows.

In the initial state, the rotors of SHED 1 and SCWT 2 are fixed. BOSD 3 is formed by the digital equivalent of the angle of rotation of the rotor of the PED 1 and SCWT 2, which, when rotated, changes in sawtooth. different laws within the synchronization zone. The input effect on the drive enters the WLL 5 in the form of a code P arriving at the first input of the adder 4. The limitations imposed on the code value of the Fn are determined by the size of the synchronization zone of SED 1 and SCRT 2 taking into account the electrical or mechanical reduction between them.

Code F0 is fed to the second input of the adder 4 ,. at the output of which the mismatch code F is formed. It arrives on. digital

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ten

15

20

35

40

45.

50

55

426

Input BS 6, from the output of which via the data bus 7, goes to PP 8, where a control signal is generated programmatically, which is sent to BS 6 via the data bus. From the BS output b, the control signal in the form of a control voltage UM is supplied to the analog outputs PCAP 9 and 10, where it is multiplied by the sine Pgip and the cosine, respectively

G -). The components of the digital equivalent / l and PG of the angle t, which is

(p-2) the smallest bits of the VQ code generated at the digital output of the BFD 3.

The trigonometric components of the TV code are obtained by means of ROM 15 and 17. At the address inputs of ROM 15, the code Y comes in direct form and the address inputs of ROM 17 in inverse pass through the block 16 of inverters containing (p-2) of the inverter. Such inclusion of nodes 15-17 allows, by using the mirror properties of a sinusoid within the quadrant, to apply standard BIS ROMs of the same type with sinus firmware, providing, in combination with the introduction of the quadrant bus 14, more efficient use of memory space. Analog signals Uga and 1P are input to the outputs of the PCAB 9 and IO and the incoming signals to the PWM inputs 11 and 12. The modulated signals from the PWM outputs 11 and 12 are fed to the control inputs of the power amplifier 13, the switching inputs of which are given a two-charge code | quadrant over the bus 14 of the quadrant formed by two higher-weight sections of the BOSD 3 digital output code 3. The F code determines the switching sequence of the windings of the SED 1 in the same way as with the step-by-step control of the SED at the main step.

Since the power amplifier 13 is close in its characteristics to a single source of current, we can assume that current signals 1 and 1 s are formed at its output. They create; electromagnetic floor vector shed | the shift of which relative to the current position of its rotor is determined by the value of and. In this case, in SED 1, an electromagnetic moment occurs, causing the rotor to move to a new position specified. code „. The control action is formed in PP 8 by assessing the divergence between the objectives.} Uu Pgy HUcjj c Rcq. inputs according to the appropriately programmed movement algorithm and the current coordinates of the drive generated by the BFD 3.

On. the input BOSD 3 information about the movements of the rotor comes in the form of analog signals and, and cos b, where it is SHON 23.

In the selector 18 quadraga eg about

and Ucg

the reference voltage Ugg and Uj.g is driven to the first

K on 00

quadrant, where and, (P

, (Uj- Uso .Uc0- When the b values are used in other quadrants, the signals Ugw and Ugj .. representing the direct or inverse values of the current values Ugg and Uj, y. The output voltages of the selector 18 are fed to the analog inputs of PDASI 19 and 20 where they are multiplied by the components of v fsf. "Pa of the output of the PCAP 20 is formed

20

and at the exit

max on the outputs of the selector 18 form the 5-th provision, providing

the formation of a signal characterizing acceleration.

The construction of the electric drive (Fig. 1) i is characterized by combining in a single device the functions of the primary converter of information control signals for the SED 1 and the secondary converter of information signals for SCRT 2. This device is a coordinate converter in which their current value is represented by the output signals of SCRT 2, and the desired is determined by the analog signal Uu. In terms of its functions, it is adequate to a differential SCHMT controlled by this analogue and signal. If the transmission coefficient P 8 is equal to 1, then the signal is controlled and

PPAP 19 .. signal and

- 2 7 rye enter differential inputs 25

amplifier 21, the output of which .forms an analog signal and

sin

(

in proportion to

thirty

35

 Usjfi cj; cyp.j.

sine difference between the current octant values given by the first octant and its digital equivalent for J, In demodulator 21, this signal is subjected to synchronous detection.

The signal also characterizes the error of the radar-tracking system, in which the selector 18, the PPAP 19 and 20 and the amplifier 21 prepares an electronic analogue of the transformer remote transmission operating in the quadrant nerve. those. For the sequential correction of its dynamic indicators is used

correction block 24. g

An analog-to-digital integrator (ACI) is used as an actuator in this tracking system, which consists of a series-connected transducer, and this implementation allows the release. PP 8 from the formation of information support for the switching process of SED 1 and facilitates the implementation of the programmed motion control algorithm. This creates certain advantages compared with the option of a unified information supply by the self-regulator.

Due to computational computing time, in PP 8, it is possible to implement algorithms not only proportional, but also proportional-integral, proportional-integral-differential, quasioptimal

At the expense of computational computing time, in PP 8 it is possible to implement algorithms not only proportional, but also proportional-integral, proportional-integral-differential, quasi-optimal

frequency 25 and the reversible counter 26 and the functional conversion or adaptive control with greater

frequently updated information and greater information capacity. This leads to improved performance and

A telephone consisting of a ROM 15 and 17 and a block of 16 inverters. The mismatch is tested by the shortest path within the quadrant and provides for reducing the signals Uj to zero.

and

Ui; At the moment when Uj Oh,;. If a corrective block 24 of an integrator is present, the electron trace system is considered.

the accuracy of the drive expands its scope.

1J increases the information capacity of the formation of the control signal SHED 1 and the digital equivalent of the transducer.

ten

,

It becomes a system with second-rate astatism. Since the digital equivalent FD of angle 0 is formed at the output of the reversing counter 26, the signal Uj at the input of the ACN is proportional to its first derivative, i.e. and the signal at the output of the demodulator is 22 and. Thus, in BOSD 3 the formation of

p ,, 00 and e.

In the described construction of BOSD 3, a higher level of information is achieved compared to the prototype.

Such an implementation allows release. PP 8 from the formation of information support for the switching process of SED 1 and facilitates the implementation of the programmed motion control algorithm. This creates certain advantages compared with the option of a unified information supply by the self-regulator.

Due to computational computing time, in PP 8, it is possible to implement algorithms not only proportional, but also proportional-integral, proportional-integral-differential, quasioptimal

or adaptive control with greater

55

the accuracy of the drive expands its scope.

The 1J increase in the information capacity of the formation of the control signal of the SHED 1 and the digital equivalent of the transducer .5

spacer by introducing quadrant bus 14 in combination with a functional transducer operating within the first quadrant. Thus, with the use of standard LSIs of the K505REZ series, an increase in the information capacity by 4 times is achieved with the same ROM volume. The introduction of the inverter unit 16 allows the use of single-type ROMs and ensures the formation of the required functional dependences both with increasing f- and with decreasing it. Due to this, movement testing is performed within the synchronization zone along the shortest path, which improves speed.

On large displacements, the speed is increased by 3-5 times.

The cumulative effect of increased accuracy and speed determines the growth rate of FEC, which increases by an order of magnitude with the use of general-purpose elements.

Dynamic accuracy is also increased in a system with variable parameters of the load on the shaft. This is achieved through the use of a compensation method of regulation, which provides a reduction in sensitivity to destabilizing factors and a better parry of external and internal disturbances.

Claims (2)

1. Closed stepper motor with self-switching and pitch fragmentation, containing a stepper motor with, a positive voltage sensor in the form of a sine-cosine rotary transformer, the outputs of which are connected to the analog inputs of the n-bit sensor signal processing unit whose digital output is connected to the second input of the adder , the first input of which is connected to the movement reference bus, the controller, the first and second permanent memories, the outputs of which are connected to the digital inputs of the first and torogo pe- remnozhayuschi: digital to analog converters, analog inputs are combined, and a power amplifier, the outputs of which are connected to corresponding inputs of the stepper elektrodviga bodies, wherein 84210 that, from a high degree of physical performance, by increasing speed and accuracy, expanding operational capabilities, an additional interface block, a two-way data bus and an inverter block are added, the outputs of which are connected to the address inputs of the second permanent memory Q devices, inputs - with the address inputs of the first constant memory of the device and with (n-2) smaller bits of the digital output code of the sensor signal processing unit, 5, the two most-worn bits of which are connected to the switching input of the power amplifier, and the interface unit is connected to the controller by a two-way data bus. 0 2. The actuator according to claim 1, about t - characterized in that the sensor signal processing unit contains a reversible counter, the converter 5 voltage - frequency, correction unit, demodulator, differential amplifier, third and fourth multiplex digital-to-analog converters and quadrant selector, the analog inputs of which are connected to the corresponding outputs of the sine-cosine rotary transformer, the switching input of which is connected to the switching input of the power amplifier the output, with the analog inputs of the third and fourth multiplexing digital-analog converters, respectively, the digital inputs of which are connected to the output the first and second permanent memory devices, and the outputs with the corresponding inputs of the differential amplifier, the output of which is connected to the information input of the demodulator, the switching input of which is connected to the reference voltage bus and the input of the sine-cosine rotary transformer, and the output connected with the input of the acceleration of the interface unit and the input of the corrective unit, the output of which is connected to the input of the speed of the interface unit and the input of the voltage converter - the frequency connected to the input of counter .reversivnogo, Ko torogo output coupled to the adder input, the input selector and the switching quadrants oschnocti input amplifier. 0 Fr FIG. 2 4f / -ts I Fr Uif Us FIG. 3