SU1506511A2 - Power amplifier - Google Patents

Abstract

The invention relates to amplifier technology. The purpose of the invention is to reduce distortion. To achieve the goal, the 1st and 2nd key amplifiers (KU) from each pair of KU 9 and additional KU 8 are made in the form of serially connected preliminary key stage 18 with amplitude collector modulation and output key stage 26, as well as the 2nd regulated power supply 27. In the power amplifier, simultaneous switching on of N pairs KU 9 and KU 8 is ensured by selecting the values of boost pulses of the base currents of transistor 25. In addition, the constant turn off delay of the key stage 26 is the same by providing the required degrees of saturation of the transistor 25 when the input signal level changes by introducing additional modulation according to the law of the envelope of the input RF signal to the key stage 18. All this leads to a decrease in phase modulation and ultimately reduces combinational actions. output RF signal. 2 Il.

Description

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31506

This invention relates to an amplifier technique and is an enhancement to an auth.-amplifier. No. 1104647.

The purpose of the invention is to reduce distortion.

FIG. Figure 1 shows a structural electrical power amplifier circuit; Fig. 2 is a diagram for explaining the operation of the power amplifier.

The amplifier contains the first amplitude detector 1, amplitude limiter 2, phase inverter 3, analog-to-digital converter (A1SCH) 4, decoder 5, N pairs of controlled keys 6, first adjustable power source 7, additional key amplifier 8, N pairs key efforts. 9, subtractor 10, first adder 11, filter 12, attenuator 13, second amplitude detector 14, second adder 15, direct current amplifier 16 (UFD), load 17, preliminary key stage 18 with am- | PLITUD collector modulation, shaper 19, delay element 20 second power source 21, switch 22, transistor 23, resistor 24, transistor 25, output key stage 26, second regulated power supply 27, first power supply 28.

The power amplifier works as follows.

When the input signal is low, ADC 4 through decoder 5, via controllable keys 6, connects the second key amplifier of each pair to the inverter output of phase inverter 3, i.e. the first and second key amplifiers of each pair excite and reverse their output signals are mutually compensated in the first adder 11. At the same time, the input signal is amplified by an additional key amplifier 8, on whose power supply voltage a voltage proportional to the output signal is supplied to the first regulated source 7. first amplitude detector 1. In the case of the envelope difference, the output

From the input signal, an attenuator 13, a second amplitude detector 14, a subtractor 10, a DCA 16 and an adder 15 to the control input of the first controlled power supply 7 provide a feedback correction voltage, reducing the difference between the envelope of the input signal.

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When the input signal reaches the first quantization level of the ADC 4, the decoder 5 connects one of the pairs of key amplifiers 9 to the non-inverting output of the phase inverter 3 via the supplied keys 6. In this case, this pair of key amplifiers is excited in phase and the output voltage of the power amplifier is determined by the total value of the output voltage additional key amplifier 8 and one in-phase excited pair of key amplifiers 9; In the case of differences in the envelopes of the output and input signals, the correction is carried out similarly time.

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But as the input signal increases, various combinations of key pairs, amplifiers 9, which are excited in phase, are connected to the first adder 11. When the input signal level changes, the output voltage and output current of the power amplifier change accordingly, and therefore the collector current of the output key stage 26 of each of the N pairs of key amplifiers 9, including the additional key amplifier 8, changes. This leads to a change in the degree of saturation of the transistor 25 output key stage 26 and, accordingly, to a change in the duty ratio of the collector voltage of transistor 25, i.e. to parasitic phase modulation (FM), as a result of which the Raman distortion (CI) of the input signal increases. In order to reduce the change in the degree of saturation, duty ratio and, accordingly, the KI level, all pairs of key amplifiers and an additional key amplifier contain an output key stage 26 and a preliminary key stage 18, to the modulating input of which is fed through a second regulated power source 27, the envelope voltage of the input RF-sig .. from the first amplitude detector 1. Thus, when the collector voltage and the current of the transistor 25 change according to the law of the envelope of the input RF signal, a change occurs simultaneously output voltage of the second regulated power supply 27, and hence the base current of the transistor 25, which ensures a constant degree of saturation and reduction

shits i (j output signal of power amplifier.

In addition, in order to reduce the CI, it is necessary to eliminate spurious FM caused by the non-simultaneous switching on and off of pairs of key amplifiers 9, which have different levels of output power.

The simultaneous switching of pairs of key amplifiers 9, including the additional key amplifier 8, is provided by a preliminary key stage 18, which operates as follows. In the initial state, at the input of the preliminary key stage 18, the level Log is set. The transistor 23 is closed. A current flows from the second regulated power supply 27 through the resistor 24, which opens the transistor 25.

At time t, at the input of the pre-key stage 18, a log level is set. 1 (Fig. 2a), having passed through the delay element 20, enters the base of the transistor 23, opening it. Through the open transistor 23 and resistor 24 a collector current flows and at the same time the reverse current of the base of transistor 25 caused by resorption of charge carriers in the base area. Due to the low saturation resistance of transistor 23, the switching time of the switching front of transistor 25 is low.

At time t, the input of the pre-key stage 18 is set to a level of Log.O.

At time t (determined by

 signal delay in real elements of the driver 19) from the input signal by the driver 19, a pulse with a duration T is formed (fig.2b), which enters the key 22, opens it and connects the second power source 21 to the collector of transistor 23, i.e. An additional current pulse flowing through the open transistor 23 is formed (Fig. 2B At time t, determined by the delay element 20, the level of the log. The input signal translates the transistor 23 to the closed state.

By this time, key 22 is not closed,

therefore, the current flowing through the open transistor 23 is redistributed to the base of the transistor 25 (Fig. 2d). The current thus generated

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The base force switches on the transistor 25, providing the required duration of the switching on front.

At time t, the output of the former 19 sets the level of the log. 0, the key 22 is opened, but the transistor 25 remains open cm due to the current flowing through the resistor 24, which provides the required degree of effect to the transistor 25. By the time tj, the process is repeated.

Thus, in the power amplifier, N pairs of key amplifiers 9 and an additional key amplifier 8 are simultaneously switched on by selecting the values of the forcing pulses of the base currents of transistor 25. In addition, the constant turn-off delay of the output key stage 26 is the same by providing the required degrees of saturation transistor 25 when changing the input signal level by introducing additional modulation according to the law of the envelope of the input RF signal into the preliminary key stage 18.

All this leads to a decrease in FM and ultimately reduces the KI of the output RF signal of the power amplifier HocTi ;.

Formula

Power amplifier by auth. No. 1104647, characterized in that, in order to reduce distortion, the first and second key amplifiers from each pair of key amplifiers and the additional key amplifier are implemented as a series-connected preliminary key stage with amplitude collector modulation, and an output key stage containing after years a connected delay element and a transistor connected in a circuit with an emitter, the input of the delay element being the input of the key amplifier and connected via a driver to the control exhibiting an input switch connected between the second power source and the collector of the transistor, is output prior yuschims key cascade with the amplitude modulation and the collector connected to the one end

150651 1

a resistor, the other output of which is the modulating input of a key amplifier and an output key stage, while the output of the first amplitude detector through the input

eight

A second regulated power source is connected to the modulating input of each of the N pairs of key amplifiers and an additional key amplifier.

Claims (1)

The claims 35 Power Amplifier Auth. No. 1104647, characterized in that, in order to reduce distortion, the first and second key amplifiers from each pair of key amplifiers and an additional key amplifier are made in the form of a series-connected preliminary key stage with amplitude collector modulation, and an output key stage containing after? well-connected delay element and a transistor connected according to the scheme with a common emitter, while the input of the delay element is the input of the key amplifier and connected through the driver to the control input of the key connected between the second power source and the collector 55 transistors, which is the output of the preliminary key stage with amplitude collector modulation, connected to one output Ί a resistor, the other output of which is the modulating input of the key amplifier and the output key stage, while the output of the first amplitude detector through the introduced second regulated power source is connected to the modulating input of each of the N pairs of key amplifiers and an additional key amplifier. 1 t ' 1 eleven • t 1 . 1 ί 1 1 1 1 Μ - ί b 1 eleven___! 1 1 " 1 J eleven  1 ! Ί ____ b to tf f is | уГ FIG. 2