SU1501101A1 - Neuron simulator - Google Patents

Abstract

The invention relates to devices for analog modeling of the nervous system and can be used in experiments in the study of neurons and neural structures. The purpose of the invention is to improve the accuracy of modeling and expand functionality by simulating the wave processes of propagation of local evoked postsynaptic potentials in the dendritic neuron fibers, taking into account the bi-directionality of the fiber. The local potentials in the form of pulsating voltages are fed from the outputs of the synapse simulation block 2 to the inputs of the dendrite simulation block 6, which are the inputs of the forward and reverse circuit adders 7 and 8. In this case, there is a propagation in the proximal direction from each activated synapse of a positive forward wave of excitation or deceleration through successively connected alternating adders 7 and delay elements 9 and a reverse wave propagating along the reverse circuit of adders 8 and delay blocks 10. In this case, the waves interact according to the signs on the entered cross-links between the forward and reverse chains of the dendrite simulation unit 6. The signal at the output of block 6 differs sharply from the simple sum of synaptic potentials that takes place in a biological object. In addition, the adjustment of delay elements 9 and 10 may reflect the characteristics of the individual morphology of the object, namely, the dendrion of a real neuron, which is also reflected on the output signal of the device and significantly increases the accuracy of the simulation. 8 il.

Description

31501101

Dam adders 7 and 8 direct and reverse circuit. When this occurs, a propagation occurs in the proximal direction from each activated synaptic, positive forward excitation wave or deceleration along successively connected alternating adders 7 and delay elements 9 and a reverse wave propagating through the reverse circuit of adders 8 and delay units 10 . In this case, the waves interact according to the signs on the entered cross-links between the forward and reverse chains of the dendrite simulation unit 6. The signal at the output of block 6 differs sharply from the simple sum of synaptic potentials that takes place in a biological object. In addition, the adjustment of delay elements 9 and 10 can reflect the features of the individual morphology of the object, namely, the dendrion of the real neuron, which is also reflected on the output signal of the device and significantly increases the accuracy of the simulation. 8 il.

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The invention relates to devices for analog modeling of the nervous system and coins to be used in experiments in the study of neurons and neural structures.

The purpose of the invention is to improve the accuracy of modeling and enhance the functionality by simulating the wave processes of propagation of local postsynaptic potentials in the dendritic fibers of a neuron, taking into account the bi-directionality of the fiber.

The goal is achieved by introducing a forward and reverse circuit, consisting of successively connected alternating three-input adders along the first non-inverting input and delay elements, in each of the simulation blocks of the dendritic fiber, and the reverse circuit begins with an adder, and the output of its last the delay element is connected via an inverter to the input of the first delay element of the direct circuit; the second non-inverting inputs of the adders of the direct circuit are connected to the inverting inputs of the adjacent totalizer The feedback circuits are the inputs of the dendrite simulation unit, the output of the direct delay circuit cannon element is connected to the second non-inverting input of the corresponding feedback adder and is the output of the dendrite simulation unit, which in turn is the device's dendritic output , and the output of each feedback delay element is connected to the third noninverting input of the corresponding forward adder.

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The direct circuit ends with a delay element whose output is the output of a dendrite simulation unit, which is connected to the inputs of an additive adder, and the inputs of each of the dendrite simulation units are connected to the outputs of the corresponding group of synaptic simulation units, to which the outputs are connected. resistive elements whose inputs are the synaptic inputs of the device.

The introduction of additional elements — adders, delay elements, and inverters connected in a certain way makes it possible to significantly improve the accuracy of modeling real neurons, especially cortices, by enabling the propagation of wave effects of propagation and interaction of local evoked postsynaptic potentials in dendrites that are not known in known devices. . The specified connection of additionally introduced elements allows the formation of dendritic outputs of the device, which greatly expands its functionality by representing the neuron as a multi-input multi-output element, and their number is individual in contrast to the known devices with one output.

The proposed device for modeling neurons, containing dendritic modeling units, makes it possible to simulate the wave processes of propagation of local postsynaptic potentials in the dendritic fibers of the neuron, taking into account bidirectional

These fibers are made in the device due to a certain combination of additionally introduced elements.

Fig. 1 shows a functional diagram of a device for modeling a neuron; Fig. 2 shows timing diagrams of the dendrite modeling unit; in fig. 3 - control points of the two-synaptic dendrite simulation unit; in fig. A - type of local postsynaptic potentials (excitatory, inhibitory, analogous, but inverted); Fig. 5 is a functional diagram (up to the level of standard functional elements) of a threshold formation unit; in fig. 6 is a schematic diagram of an output pulse driver; in fig. 7 is a functional block diagram of feedback; in fig. 8 is a functional block diagram.

A device for simulating a neuron (Fig. 1) contains controllable resistive elements 1, synapse modeling blocks 2, matching amplifiers 3, accumulative elements 4, delay elements 5 connected in series and forming synapse modeling blocks 6 of three dendrites modeling - input adders 7 and 8 and delay elements 9 and 10, forming a forward and reverse circuit, respectively, and having dendritic outputs 12, an additive adder 13, whose inputs are connected to the outputs of blocks 6, the threshold unit 14, is turned on The output of the adder 13, block 14 consists of a comparison element 15, the input of which serves as an input of a block 14, a block 16 for generating a threshold, the output of which is connected to the second input of a block 15, a former 17 output pulses connected to the output of the block feedback block 18, the output of which is connected to the input of the block, 16, and the input is connected to the output of the device, which is the output of the block 17, the synchronization block 19, the input of which is connected to the output of the device, the outputs of the synchronization block are connected to the control inputs resistive elements 1.

The neuron simulator works as follows.

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The input signals in the form of the spike following frequency are fed from the device inputs through controlled resistive elements 1, where they are scaled in amplitude according to the weight of each synaptic contact, to the inputs of the simulating and inhibiting synapses 2, which are the inputs of the corresponding synaptic contacts. matching amplifiers 3, from the outputs of which the pulse sequences arrive at the storage elements 4, where the shape and duration of the pulses change, and their sign depends on the presence or absence of inversion in the elements 4 (excitation obstructive or synapse).

The signals are then fed to the inputs of delay elements 5, which simulate a delay in the release of a mediator in the corresponding synapse, the outputs of which are the outputs of synaptic modeling units 2, grouped into groups, each of which simulates synapses located on one dendrite.

The received signals of local excitatory and inhibitory postsynaptic potentials (PSIs) from the outputs of blocks 2 of the synapse simulation of one group are fed to the inputs of one dendrite simulation block 6 according to their location on the dendrite of a real neuron. The local SRP signals from each synapse are received from the inputs of units 6 of simulation of dendrites to the second non-inverting inputs of adders 7 of the direct circuit, forming a direct wave of dendritic potential with a plus sign propagating in the forward direction along the direct circuit, and to the inverting inputs of the adder 8 a reverse circuit to form a wave of a dendrite potential with a minus sign propagating in the opposite direction along the reverse circuit. At each adder 7 of block 6, the input signal from the output of the corresponding block 2 of the synapse simulation with the direct wave of the dendritic potential propagates along the direct circuit in accordance with the damping factor set by the transmission coefficient of elements 9 delayed

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and "entering the first non-inverting inputs of adders 7 from the codes of 9 elements for;) and subtracting the backward wave propagating along the reverse circuit from synapses to the right and entering the third non-inverting inputs of adders 7. The resulting signals propagate in the forward (proximal) direction to the output of the dendrite simulation unit 6 through delay elements 9 and right adders 7 and is a direct wave of dendrite potential. On each adder 8 of the dendrite simulation unit b, the inverted input signal is summed, arriving at the inverting input from the output of the corresponding synapse 2 modeling unit 2, and the inverted back wave fed to the first non-inverting input of the adder 8 from the output of delay element 10 and subtracting them from noninverted direct wave arriving at the second noninverting input (since the latter has the opposite positive sign) ,. The resulting signals propagate in the opposite direction (dnstalnom) until they reach the inverter 11, where, changing sign, come from its output to the input of the element 9 of the delay of the direct circuit, i.e. converted into a direct wave, which models the reflection of reverse waves of a dendritic potential from the distal end of the dendrite. .

Thus, the signal from the output of the dendrite simulation unit 6 reflects the complex interactions of the forward and reverse waves of the dendrite potential. and, as in a real neuron, is not equivalent to a simple sum of delayed signals from the outputs of synaptic modeling blocks, which significantly increases the accuracy of modeling thin neurophysiological phenomena in dendritic ones. structures.

In addition, the outputs of the 9 delayed circuit elements 9 are dendritic outputs 12 of the device, which allows connecting them to the inputs of other dendritic simulation units 6 (instead of synapse simulation units 2) to simulate electrical nerve cell dendrion synapses, which is extremely common in neurons with advanced dendrion.

FIG. 3 shows control points in a functional diagram of a dendrite simulation unit 6; for simplicity, a two-input model block is shown.

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vanilla dendrite with blocks 2 simulating excitatory synapses; Fig. 2 shows timing diagrams at the control points of the response of the dendrite simulation unit 6 to voltage surges on two inputs; in fig. 4 shows a timing diagram of a single local SRP at the output of the synapse modeling unit 2.

In this case, the static transfer coefficients of the elements 9 and O of the delay are 0.5.

In the diagram of FIG. 3 one can observe (at point I — output of block 6, as well as at points D and J — dendritic outputs of block 6) the repeated transmission of the voltage jump, resulting in interaction of reactions from two or more synaptic inputs (A, b) in time with the consequence and distribution of this complex signal in both directions on the dendrite. The propagation is modeled by time inter-synaptic interval discretization by connecting the synapse contact points with the forward and reverse side delay lines.

Thus, the proposed device, in contrast to the well-known models, simulates the non-equivalence of the signal at the dendrite output to a simple algebraic sum of ICP from separate synapses, similar to a real neuron by taking into account wave processes in dendrites, implemented as described.

The resulting signals from the outputs of the dendritic modeling units 6 are fed to the inputs of the additive adder 13, in which they are algebraically and temporarily summed. The total signal from the output of the adder 13 is fed to the input of the threshold unit 14, i.e. to the first input of the comparison element 15, to the second input of which a signal is received, equal to the threshold value from the former of the threshold 16.

If the sum signal from the output of the adder 13 does not exceed a certain initial threshold value specified by the second input of the comparison element 15 from the output of the threshold shaper 16, then the output voltage of the shaper 17 of the output pulses is absent. When the total signal from the adder 13 exceeds the threshold value in the comparison element, the voltage appears at the output of the latter;

it is proportional to the voltage from the output of the adder 13. The voltage from the output of the reference element is fed to the input of the imager 17 output pulses, generating1 pulses, which are similar in shape to the spikes of a real neuron, and their frequency is proportional to the voltage applied to the input of the imager 17 high impulses ..

Adaptive adjustment of the neuron model is carried out similarly to the prototype using the feedback block 18, the threshold former 17, and the synchronization block 19. In this case, with the appearance of a pulsation at the output of the device, the feedback signal is fed to the input of the feedback unit 18, the output of which is a signal arriving at the input of the threshold generator 17, resulting in an increase in the value of the threshold supplied as voltage the second input element 15 of the comparison. In addition, the signal from the output of the imaging unit 17 of the output pulses is also fed to the input of the synchronization unit 19, the i-th of the remaining inputs receives a signal from the i-th input of the device.

Depending on the satisfaction of the given conditions with the given conditions, from the block: 19 synchronization, a control signal is received, which changes the resistance of the 1st controlled resistor

element 1. The device is tuned by selecting the transfer coefficients (always less than one) and the time constant of the delay elements 9 and 10 equal to each other in pairs. Thus, the parameters of forward 9 and inverse 10 delay elements are the same in pairs and in the general case differ from the neighboring pair, which corresponds to different distances between the synapses and fiber heterogeneity.,.

FIG. 5-8 show the functional elements up to the level of standard elements and schematic diagrams of blocks 16-19, respectively.

The threshold shaping unit 16 (FIG. 5) may consist of an adder 20 and a p-stand voltage source 21, the output of the adder is the output of block 16, the first input of the adder 20 is its input, and the second input of the adder 20 is connected to way out

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reference voltage source (ION)

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The output pulse shaping unit 17 (FIG. 6) can be performed on an operational amplifier (op-amp) 22, a field-effect transistor 23, capacitors 24 and 25, resistors 26-29, a diode, 30, a Schmidt trigger 31, and a key 32. Op-amp 22, transistor 23, capacitors 24 and 25 and resistors 26-29 form a voltage generator 33 controlled by a voltage, and transistor 23, a capacitor 25 and resistors 28 and 29 form a controllable resistive element 34 of the time of the pulse generator circuit.

Block 17 works as follows. If a negative voltage is applied to the input of the block, the diode 30 is closed, the voltage at the input and, accordingly, the output of the trigger 31 is zero, the key 32 is in the open state and there is no pulse at the output of the block 17. If the voltage at the input of the block 17 becomes greater than zero, the diode 30 opens and a voltage equal to the input appears at the trigger input, which switches it to a state of logical one, which, coming to the control input of the key 32, closes it In this connection, the output of the op-amp 22, which is the output of the pulse generator 33, is connected to the input of the blinker. The pulse generator 33 is a conventional relaxation generator, the oscillation frequency of which is determined by the capacitance of the capacitor 24 and the drain-source resistance of the transistor 23: f -. 2.2R |., C, 2.j. With an increase in the positive side, the voltage at the input of the block 17, i.e. the voltage across the gate of the transistor 23, the resistance of the latter channel decreases linearly, which leads to a linear increase in the frequency of the pulses at the output of the block 17. Resistors 28 and 29 and the capacitor 25 are needed to increase the linearity of the characteristic of the controlled resistive element 34. If necessary, frequency ranges can be are fitted by applying a negative bias to the gate of transistor 23 (in this case, it is necessary to separate diode 30 and generator 33, for example, connecting diode 30 to resistor 29 via an emitter follower ).

The feedback unit 18 (Fig. 7) consists of a series-connected matching element 35, a low-pass averaging filter 36 and a scaling amplifier 37. The input of the block is the input of the matching element 35, and the output is the output of the scaling amplifier 37.

At the appearance of pulses at the output of block 17, a voltage appears at the output of filter 36, which is proportional to the pulse frequency. This voltage is scaled by amplifier 37 depending on the adaptive properties of the particular neuron and is fed to the input of block 16, where, Your adder 20 with the voltage of ION 21 is converted to a threshold voltage. This feedback block 18 implements the linear law of neuron adaptation. If necessary, depending on the specific biological analogue, a nonlinearity can be introduced into the feedback of the amplifier 37, which will study the properties of a particular type of neuron.

The synchronization unit 19 (FIG. 8) consists of N + 1 matching elements 3 (N is the number of synaptic inputs), N adders 39, N + 1 low-pass filters 40, N logic circuits 41, control N keys 42, and storage capacitors 43.

The N matching elements 38 are the inputs (synaptic) of block 19

connected to the synaptic inputs of the logic of logic circuits 41,

the devices, the outputs of these elements 38 are connected via low-pass filters 40 to the first inputs of adders 39, whose outputs are connected via keys 42 to the outputs of block 19, in parallel with which are connected storage capacitors 43, the second inputs are combined and connected to the output of low-pass filter 40, whose input connected

and each logic circuit is supplied with a voltage proportional to the frequency of the input pulse sequence, which arrives at c 40 The corresponding synaptic input (exciting or inhibiting), and at a voltage proportional to the frequency of the output signal of the device. If these frequencies are constant, the voltage

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through a matching element 38 with an input 45, the output of the differentiators 44 are equal to the nu- (axon) block 19, which is connected to any. At the same time, the voltages at the outputs axonn1m the output of the device, the outputs of the low-pass filters 40 of the synaptic inputs of block 19 are connected to the first inputs of logic circuits 41, the output of the filter 40 of the axon inputs of block 19 is connected to the second inputs of logic circuits 41, the outputs of which are connected to control inputs of the corresponding keys 42.

Logic circuit 41 contains two differentiators 44, two Schmidt flip-flops 45, circuit 46, and the inputs of the differentiators are the first and

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Triggers 45 are also equal to logical zero. If the frequency of the input pulse sequence changes at any synaptic input at the outputs of the differentiators 44 connected to the inputs of block 19 through blocks 38 and 40, a voltage appears, which leads to the triggering of the triggers 45 connected to them connected to the first inputs of circuits I 46. Triggers 45 connected to the second inputs of circuits I 46 operate (at the output a unit signal appears) analogous to

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the second inputs of the logic circuit 41, and their outputs are connected via triggers 45 to the two inputs of the circuit 46, the output of which is the output of the logic circuit 4.

Block 19 provides for the reproduction of adaptive responses of the neuron to such changes in the frequency of the input pulse sequences received via synaptic inputs, which lead to changes in the frequency of the output pulses, and block 10 realizes the resistance of the neuron to changing its state, i.e. addictive reaction. Voltage at the i-th output of the block

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the frequency of the input pulse sequence at the 1st input; the frequency of the pulse sequence at the sleep output.

The average values of the frequencies are allocated by the filters 40 and fed to the adders 39 in the form of voltages proportional to the values of the frequencies.

In block 19, the synchronization signals from the outputs of low-pass filters 40 (frequency converters to voltages) are supplied as voltages proportional to the frequencies of the input and output signals, and the voltage 34 proportional to the frequency of the input pulse sequence arriving at the associated synaptic input (exciting or braking), and a voltage proportional to the frequency of the output signal of the device. If these frequencies are constant, the voltage

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The 45 outputs of the differentiators 44 are equal to zero. In this case, the voltage at the outputs

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Triggers 45 are also equal to logical zero. If the frequency of the input pulse sequence changes at any synaptic input at the outputs of the differentiators 44 connected to the inputs of block 19 through blocks 38 and 40, a voltage appears, which leads to the triggering of the triggers 45 connected to them connected to the first inputs of circuits I 46. Triggers 45 connected to the second inputs of circuits I 46 operate (at the output a unit signal appears) analogous to

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Thus, in case of a change: the frequency of the device output pulses, the signal of a logical unit appears at the outputs of the AND circuits 46 only those logic circuits 41 which correspond to those synaptic inputs whose input signal frequency is currently changing under the condition of a change in the output signal of the device. This leads to the closure of the keys 42 corresponding to these synapses, and the jcyMMapHux signals from the outputs of adders 39 through the keys 42 and capacitors 43 to the inputs of controlled cutting elements 1, changing their resistance in the direction of decreasing nna This reduces the contribution of input frequency effects varying in frequency to the formation of the output signal, which also leads to a decrease in its frequency variations, i.e. to stabilize it. Thus, block 19 simulates the neuron's habituation to variable in frequency input signals, realizing parametric stabilizing negative feedback. Block 19 works equally for both excitation and decelerating signals. In this case, the change in frequency of the input signal, regardless of its sign, is important. Technically, this is realized by the fact that the blocks 38, which are connected to the exciting inputs, are non-inverting, and to the braking inputs — the inverting device.

Conventional field-effect transistors can be used as control resistive elements 1. At the same time, control signals from capacitors 43 (Fig. 8) are applied to their gates, which leads to a change in the source-drain resistance. At the same time, the source-drain resistance almost linearly depends on the control signal. Transistors can be switched on} both in series and in parallel in the form of a voltage divider. The capacitors 43 serve to maintain the residual voltage (and, therefore, the resistance of the resistive elements 1) when switching off the keys 4.2

Thus, the proposed device, by introducing additional elements connected in a certain way, makes it possible to simulate wave processes occurring in the dendrites of the re

nealnyh neurons. This is especially important when modeling neurons with a developed dindrione, such as, for example, pyramidal neurons of the new cerebral cortex, Iurkinje cells of the cerebellum, etc., since with the developed dendrione, the main processing of information occurs in dendritic fibers.

Due to the execution of dendrite simulation blocks in the form of interconnected forward and reverse circuits, consisting of alternating three-input adders and delay elements,

it is possible to simulate the wave processes of local PSI propagation along the dendritic fiber in both proximal and distal directions, as well as the possibility of reproducing complex interactions of propagating waves and the effect of synapses on each other depending on their mutual arrangement with a relatively small number of similar elements , which significantly improves the accuracy of modeling thin neurophysiological processes in a real neuron.

Ease of moving a signal from any

the points along the dendrite simulation block allow using these points as outputs and simulate dendritic dendritic synapses of both chemical and electrical type, i.e.

present the neuron model not only as a multi-input (traditional representation), but also as a multi-output, which greatly expands the functionality as a separate model

neuron, and when modeling neural networks.

Thanks to the fact that by pairwise changing the parameters of the elements of the forward and reverse circuits in the blocking

kah simulate dendrites easy

the morphological features of the mutual arrangement (and, consequently, their mutual influence) of the synapses on the dendrite are readable; the flexibility of the neuron model is significantly increased.

Expansion of functionality, as well as increased accuracy, flexibility and versatility of the proposed device, allow the model 55

vat a wider class of thin neurophysiological phenomena. This allows the simulation of neural networks of various brain regions, the individuality of which is reflected

15150110

the corresponding switching of the device I / O and the add-ons of the parameters of the delay elements, therefore, makes it possible to use in experiments one neuron model for a fairly wide class of tasks, reducing the cost of creating new neuron models for each particular case

Claims (1)

Invention Formula A device for simulating a neuron, containing dendritic modeling units, synaptic modeling units, consisting of a series-connected matching amplifier, accumulator and delay element, the output of which is the output of my 2nd circuit, the second non-inverting synapse modeling unit, and the last input of the matching synapse element, controlled resistive elements, whose inputs are device inputs, outputs are connected to the input of a synapse modeling block, an additive adder, whose inputs connected to the outputs of the dendrite modeling unit, and the output to the input of a threshold unit consisting of a series-connected feedback unit, a threshold shaping unit, a comparison element and an output pulse shaper, the output of which is the output of the threshold block g of the direct circuit, terminating element and the output of the device and connected to the delay volume, the output of which is through the feedback unit and the threshold shaping unit to the second input g of the reference element, and the synchronization unit, the outputs of which are connected to the pack output unit simulation dendrite connected to the additive combiner, and inputs ka zdogo of the blocks of the simulation of dendrites 40 are connected to the outputs of respective groups of units simulate synapses. equalizing inputs of resistive elements, and inputs - with inputs and outputs five the house of the device, which differs from the fact that, in order to improve the accuracy and enhance the functionality, the direct and reverse circuits are inserted into each of the simulation blocks of the dendrite, r consisting of successively connected three-input adders and delay elements, - in each of the circuits, the output of the previous adder is connected to the input of the next delay element, the output of which is connected to the first non-inverting input of the next adder, while the reverse circuit starts from the adder, and the output its last delay element is connected through an inverter to the input of the first delay element rows adders straight straight- chain connected to the inverting inputs adjacent to them and return circuit of adders are input modeling unit; 25 of the dendrite, the code of each forward circuit delay element is connected to the second non-inverting input of the corresponding feedback adder and is the output of the day 30 drit modeling unit, and the output of each feedback delay element is connected to the third non-inverted input corresponding adder a straight circuit terminated by a delay element whose output is with the output of the dendrite simulation block connected to the additive adder, and the inputs of each of the dendrite simulation blocks are connected to the outputs of the corresponding group of synaptic simulation blocks. cpua.2 Phie lsp 5 Ljl3 (ft. in cpus.7 one