SU1499463A1 - Tolerance check device - Google Patents

Abstract

The invention relates to a pulse technique and can be used in digital measuring devices, analog converters, as well as automatic voltage control devices. The aim of the invention is to expand the field of application by ensuring that a signal is formed on the corresponding output bus depending on the polarity of the input signal, the value of which is within a certain tolerance. The tolerance value is set using a comparator 1 and resistors 5, 12, 13. The input voltage is compared to the lower and upper tolerance limits using comparators 2, 3, which control the operation of transistors 8, 9, whose collectors are connected to output buses 10 , 11, at the outputs of which pulses are formed depending on the polarity and the magnitude of the input voltage. 2 Il.

Description

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The invention relates to a pulsed equipment and can be used in digital measuring devices, ana- log converters, as well as in automatic voltage control devices.

The aim of the invention is to expand the field of application due to the possibility of forming on the corresponding output bus depending on the polarity of the input signal, the value of which is within a certain tolerance.

FIG. 1 shows a block diagram of the device; .on FIG. 2 - timing diagrams for the operation of the device.

The tolerance control device contains three comparators 1-3, input bus 4, the first - the third resistors 5-7, two transistors 8 and 9, output buses 10 and 11, quarter 12 and fifth 13 resistors, while the non-inverting inputs Comparators 1-3 are connected to the input bus 4, the inverting input of the first comparator 1 is connected to the common bus, and the output to the first output of the first resistor 5, the outputs of the second 2 and third 3 comparators are connected via the second 6 and third 7 resistors to the bases of the first 8 and second 9 transistors, respectively, whose collectors are connected s with output buses 10 and 11, while the inverting inputs of the second 2 and third 3 comparators are connected respectively to the first terminals of the fourth. the correct 12 and the fifth 13 resistors connected in series with the first resistor 5..

The device works as follows.

At time t, (Fig. 2), the input voltage of the positive residual field has a value less than the lower acceptable value. At the output of the comparator 1, a positive polarity voltage is formed, which supplies the voltage divider across the resistors, the voltage value on the resistor 13 sets the lower tolerance threshold, and the voltage value on the resistor 12 sets the upper voltage tolerance value

Due to the fact that the input voltage is less than the voltage values applied to the inverting inputs of the comparators 2 and 3, the voltage from the output

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KONmapaTOpoB 2 and 3 are missing. (Comparators can be used with the saturation voltage level of O, + or with +5 -) and Comparator 1 is used with the nash level (esh-1 -, +.

There are no voltages on the output tires 10 and 11 either.

At time t (Fig. 2), the input-voltage value exceeds the value of the lower setpoint level, therefore, at the output of the comparator 2, a high positive level is formed, from which transistor 9 saturates the base current flowing through the resistor 7. On the OUT bus 11, a positive potential is formed, indicating that the input voltage of a positive polarity and its value are between the values of the large and small tolerance values.

At time t. (Fig. 2) the magnitude of the input voltage exceeds the magnitude of the larger setpoint; at the outputs of Comparators 2 and 3, positive polarity voltages are formed, transistors 8 and 9 are locked and output signals on buses 10 and 11 are absent.

During the time from t to tg. (FIG. 2), in a similar manner, a high potential is formed on the output bus 11, indicating that the magnitude of the input voltage for the female is within a given tolerance,

At time tg (Fig. 2), the input voltage is less than the lower value of the setpoint and has a negative polarity, therefore, the inverter inputs of the comparators 2 and 3 have negative setpoint voltages and positive voltages are present at their outputs rnness.

At time t, the input voltage exceeds the voltage of the lower setpoint, therefore, at the output of the comparator 2, the voltage is close to zero, the transistor 8 is saturated and a positive voltage is formed at the output pin 10, which indicates that the input voltage has a negative polarity and its value is within the specified tolerance.

Similarly, the output signal is generated on bus 10 and over time from

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Claims (1)

Invention Formula The tolerance control device contains two comparators, the inverting input of the first of which is connected to the common bus, the non-inverting input to the input width and the output to the first output of the first resistor, the output of the second comparator is connected via the second resistor to the base of the first transistor, the collector of which is connected to the first output bus, characterized in that, in order to expand the scope of application by ensuring that a signal is formed on the corresponding output bus, depending on the polarity of the input signal, orogo is a certain tolerance, it introduced a third comparator, third, chet- the second and the second transistor and the second output bus connected to the collector of the second transistor a, the base of which is connected via a third resistor to the emitter of the first transistor and the output of the third comparator, the non-inverting input of which is connected to the input bus and non-inverting input of the second operational amplifier the output of which is connected to the emitter of the second transistor, and the inverting input of the third comparator is connected to the second inlet of the first resistor and the first terminal of the fourth resistor, the second terminal of which It is connected to the inverting input of the second comparator and the first terminal of the fifth resistor, the second terminal of which is connected to the common bus. V ty ir 8% 10 Фа9.1