SU1493989A1 - Control unit of electric power converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used in voltage or current stabilizers, as well as in devices for converting direct current energy to direct current or alternating current energy, the regulating node of which is built on N parallel-connected transistors. The purpose of the invention is to improve the dynamic characteristics by increasing the accuracy of the distribution of currents and power between parallel-connected circuits while increasing the efficiency. The device contains N parallel-connected transistors, the emitter circuits of which include the same resistors, as well as N -inverted inverter adder, differential amplifier, N two-input inverting adders and N-channel turn-on delay circuit, which automatically establish a uniform distribution of currents and powers of parallel-connected transistors. 2 hp f-ly, 1 ill.

Description

31D93989

the input power bus, and the free terminals of the resistors are connected to the output power bus of the device, connected in series with the N-input inverting adder 3, whose N inputs are connected to the emitters of the transistors, and the output is connected to the bus for connecting the total current meter, differential amplifier 4, non-inverted -) which is connected to the output of the inverting adder 3 and. bus for connecting the total current meter, and the inverting input is connected to the bus for connecting the control signal source, as well as the control unit, which includes N two-input inverting adders 5.1-5.N, one input of each of which is connected to the output of - 20 of the secondary amplifier 4, the second inputs of each of the adders are connected to the emitters of the respective transistors, and the outputs of each of the inverting adders are connected to the bases 25 of the respective transistors via the N-channel switch-on node 6.

The regulatory electrical energy conversion unit operates in the following manner.

A power supply is applied to the input power bus. At the same time, the bus for connecting the source of the control signal is supplied with the voltage V, which is fed to the inverting input of the differential amplifier 4, where it is inverted. Inverted control voltage —Vo is supplied to the inverting sum- 40 tori 5.1 (i 1, N), where it is re-inverted and amplified K times. The modulus of the transmission coefficient of the differential amplifier 4 rapen unit. After the second inversion and laziness in the inverters 5.1 of the voltage K V, the N-channel node 6 of the turn-on delay enters the bases of the transistors l.i. As a result, through each of the transistors d l.i. As a result, a current Ij flows through each of the transistors l.i, which creates a corresponding emitter resistor 2.i (1 I.N).

with low resistance R, voltage drop V IjuR. . The inverting-adder 3 performs the summation of voltages on the emitter resistors 2.i with weights 1 / N and forms at its output a voltage whose value is directly proportional to the average current Ij-p (as well as to the total current) through transistors l.i

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The output signal from the inverting adder 3 is fed to the bus to connect the total current meter, which is directly proportional to the average current flowing through the transistors of the regulator unit of the electrical energy converter, as well as to the non-inverting input of the differential amplifier 4. The differential amplifier 4 generates a difference signal at its output

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arriving at one of the inputs of each of the inverting adders 5.i. Each inverting adder 5.i combines the signal from the output of differential amplifier 4 with the voltage from the corresponding emitter resistor 2.i — current sensor, amplification K times and inverting the total signal. As a result, at the output of each of the inverting adders 5.i, a control signal Vy is generated; the corresponding transistor l.i, consisting of the sum of the current control signal of the transistor l.i (K-V), and the error signal (K UV (), aimed at reducing the difference between the average current through the transistors and the current through the transistor 1 .i

V. -K (,) K-Vj, + K-R / Iep- -I.) K-V, - K - uVy. .

The transistor control signals l.i from the outputs of the inverting adders 5.i come through. N-channel node 6 turn-on delay on the base of the corresponding transistors l.i. During the operation of the device, the H-channel node 6 of the turn-on delay transmits all N input signals to the corresponding outputs with a transmission coefficient close to one. However, when connecting the supply voltage to the device, at the initial moment of time5U9

Neither due to transient processes in all inverter summers, differential amplifier 4, as well as in the power supply circuits of the device, the outputs of some inverter 5.1 adders can cause signals opening for a short time one or more transistors l.i. This can lead to the withdrawal of the corresponding open transistors l.i from the system (due to the flow of current exceeding the permissible current) or load (due to the fact that the current through it can be much higher than the required one). Therefore, the N-taped switch-on delay unit 6 delays the supply of opening voltage from the outputs of inverting adders 5.1 at the time of transient processes in all adders, differential amplifier 4 and power supply circuits after connecting the circuit to the power supply sources to the inputs ( base) tra transistors 1.i

Compared with the control unit of the known device, this device, due to the supply of a control signal simultaneously to all control transistors, allows for a much more uniform dynamic distribution of currents and powers between parallel-connected transistors. Since in the regulating node of a known device, the control signal is first fed to one transistor and then to the others, then, with a sudden change in the control signal or load, during the delay time of the supply of the signal to everything except the first transistor, the current through the first transistor can appear to be substantially more currents of the remaining transistors. If at the same time the current through the first transistor turns out to be greater than the maximum permissible pulse current for this type of transistor, then it can fail. Thus, in a dynamic mode, during the delay time of the signal to the other transistors, a significant part of the entire load current can flow through a single first transistor. Therefore, the maximum load current for such a device can not be significantly higher than the maximum permissible pulse current of a single transistor. max-LL of this device, due to the simultaneous operation of all transistors, the pulsed current in the load can reach

1 IMP N - N UMP. In addition, due to the introduction of the N-channel switch-on delay node, the described device eliminated the previously mentioned deficiency of the regulating node of the prototype device, which is associated with poor dynamic characteristics when it is connected to a power source.

Claims (3)

1. The regulating unit of the electric power converter containing N parallel-connected circuits consisting of a series-connected transistor and a resistor connected by one output to the emitter of the transistor, the collectors of the transistors are connected to the input power bus, and the free terminals of the resistors to the output power bus and the unit controlling the transistors with N inputs and N outputs connected to the bases of the transistors, the transistor controlling block including N comparison and amplifying nodes, the first input of each of the nodes In, with the exception of the first, it is connected to the emitter of the corresponding transistor, characterized in that, in order to improve the dynamic characteristics by increasing the accuracy of the distribution of currents and powers between parallel connected circuits, an N-input inverting adder is added to the control unit, the inputs of which are connected to the emitters of the corresponding transistors, and a differential amplifier, one input of which is connected to the output of the inverting adder and the other to the bus for connecting the control source and the comparison and gain nodes are made in the form of two-input inverting adders, the first input of the first of which is the first input of the first comparison and gain node connected to the emitter of the first transistor, and the second inputs of all two-input inverting totalizers are the second inputs of all nodes comparison and amplification connected to the output of the differential amplifier, and the outputs of the two-input inverting adders are connected to the bases of the respective transistors, 2. The regulating unit according to claim 1, characterized in that an N-channel switch-on delay node is inserted into the transistor control unit, with the outputs of the two-input inverting sum- The mators are connected to the bases of the respective transistors via an N-kaHanbHbift turn-on delay node. 3. A regulating unit according to claim 1, characterized in that a bus is inserted in it for connecting a total current meter connected to the output of the N-input inverting adder. Tire KOMgfIt Wwmmtpa tire