SU1490723A1 - Receiver of digital high-speed phase-shift keyed signals - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to improve noise immunity. The receiver contains spacing channels 1, each consisting of an adaptive transversal filter 2 and an adjustable amplifier 3, a phase demodulator 4, an adder 5, a decision block and error detection unit 6, an adaptive feedback transverse filter 7, a control block 8, a block 9 synchronization, automatic gain control unit 10, control signal generation unit 11, adjustable feedback amplifier 12 and radio signal adder 13. Input signals through channels 1 are fed to adder 13, where they are linearly summed. Next, the received signal is subjected to phase demodulation and is fed to the adder 5, where the intersymbol interference interference is compensated. The decision and error determination unit 6 from the received signal generates an output information signal and an error signal. The goal is achieved by the introduction of a formation unit 11 and an amplifier 12, with the help of which a compensating interference voltage, determined by the signal-to-noise ratio in the channel, is formed. 3 il.

Description

or

Yt, S (M, Cp, S t) (, (, t) n (t) 3 1, n

Y (t) (U, (t) LocCos GD t -t-9;) c () „(tM ,,, (t) n (t),

de (TS (t),), a multiplier characterizing the attenuation during the passage of a signal (interference by the ISI) over the propagation channel, i.e., the amplitude component of the transmission coefficient of the Vth diversity channel;

CJ, GDn is the carrier frequency of the signal (MCI interference);

-With -in Array phase shift of the signal (MCI interference) in the -th diversity channel;

n (t) is an additive white noise interference; informational

signal parameter (MCI interference).

At the output of the radio signal adder 13, a resultant signal is obtained that is driven to the same frequency and phase.

At the output of the phase demodulator there is a video sequence

S, S (KT) R., X, + and.,

/ t

Defc - impulse response of the system;

Xj, - information sequence;

and and +

+ n (t) is the disturbing effect of noise.

The asterisk denotes the convolution operation, continuous or discrete.

At the output of the decision block 6 and the determination of the error, the solutions X | are obtained, corresponding to the values O or 1. In addition, in the block 6 of the decision decision and the error determination, the operation of checking the conformity of the decision X | the value of the current value of S | signal. Based on the video sequence S 1 and errors L, the weights of the adaptive transverse feedback filter 7 (gi) and the weights of the adaptive transverse filters 2 (pc) of the corresponding diversity channels are formed.

Thus, on the basis of previously adopted decisions, X | In the adaptive feedback transversal filter 7, the voltage of the intersymbol interference tails from previous pulses is formed, compensating for this interference in the received sequence.

Consequently, at the output of the adaptive transverse filter 7 feedback, the value of the intersymbol interference voltage (flio, (pp,)), formed on the basis of jtio, Fp, L, XK estimates, is obtained.

This algorithm minimizes the standard deviation between the input signal arriving at decision block 6 and determining the error, and the transmitted signal.

However, taking into account errors at previous clock intervals, the signal at the output of the adaptive transversal feedback filter 7 does not always have the desired correct values, which leads to an increase in the likelihood of subsequent errors, resulting in an avalanche-like increase in errors.

To reduce the multiplication effect of an avalanche-like increase in errors, in the case of a single wrong decision, especially with a small signal-to-noise ratio at the input, leading to threshold effects in the adaptation system, a control signal generating unit 11 and an inverse amplifier 12 are introduced into the receiver connection. On the basis of the voltage of 25 SRI O or 1 C + Ug) and the voltage from the output of the control voltage generating unit 11 TUg, an analog feedback voltage is formed, allowing more accurate generation of the compensation voltage of the MCI, in this In this case, the weight feedback algorithm is implemented. When the signal-to-noise ratio at the input of unit 11 decreases, the level of analog feedback voltage automatically decreases, as a result of which the receiver proceeds to a gradual decrease in the compensation voltage of the MCI interference and even to an automatic deviation of the compensating voltage upon the disappearance signal, preventing , the effect of the occurrence and multiplication of errors due to

35

hard feedback by decision.

channel: in-phase and mid-phase (containing a signal shifted by half a clock interval). The in-phase channel consists of an integrator 21, a comparator 22, a detector 23, and a non-phase channel media contains an integrator 14, an analog-to-digital converter 15 and a delay element 16. The outputs of the detector 23 and the delay element 16 are connected to the inputs of the digital multiplier 17, the output of which is connected via serially connected digital adder 18, the controlled oscillator 19 and the control element to the control inputs of the integrators 21 and 14 of the common-mode and mid-phase channels. The common-mode and mid-phase channel inputs are combined and are the input of the synchronization unit 9, to which the signal from the unit 6 is supplied, and the output of the delay element 16 is the output of the synchronization unit 9

Block 6 works as follows (fig.Z). The video signals from the output of the adder 5 are fed to the filter 25, where the strip-matched filtering is performed. From the output of the filter 25, the filtered signal is fed to the input of the synchronization unit 9 and to the block 26, where the analog value of the signal corresponding to the pulses is sampled and stored.

gating generated in synchronization unit 9.

Gated pulses from the output of block 26 are fed to a two-threshold comparator 27 and a differential amplifier 24. From the output of a two-threshold comparator 27, a calibrated and regenerated binary signal is sent to the output of block 6 and simultaneously and not to the same differential input

Amplifier 24, at the output. This is due to the fact that the GF FM for which an error signal is generated, on the basis of an error communication, most often, an error signal is formed in accordance with the expression

When converting a useful signal by noise into a small signal, but already opposite to the polarity. Therefore, it is desirable that the absolute value of the envelope of the received signal at the input of the block 11 is hidden in the feedback circuits during compensation.

The synchronization unit 9 (Fig. 2) is in the l-unit clock synchronization unit and can be implemented on the basis of the in-phase-phase circuit. In block 9 synchronization work like two

O 0

five

channel: in-phase and mid-phase (containing a signal that is shifted by half the clock interval). The in-phase channel consists of an integrator 21, a comparator 22, a detector 23, and the middle-phase channel contains an integrator 14, an analog-to-digital converter 15 and a delay element 16. The outputs of the detector 23 and the delay element 16 are connected to the inputs of the digital multiplier 17, the output of which is connected via serially connected digital adder 18, the controlled oscillator 19 and the control element to the control inputs of the integrators 21 and 14 of the common-mode and mid-phase channels. The common-mode and mid-phase channel inputs are combined and are the input of the synchronization unit 9, to which the signal from the unit 6 is supplied, and the output of the delay element 16 is the output of the synchronization unit 9.

Block 6 works as follows (fig.Z). The video signals from the output of the adder 5 are fed to the filter 25, where the band-wise filtering is performed. From the output of the filter 25, the filtered signal is fed to the input of the synchronization unit 9 and to the block 26, where the analog value of the signal corresponding to the pulses is sampled and stored.

gating generated in the synchronization unit 9.

Gated pulses from the output of the block 26 are fed to a two-threshold comparator 27 and a differential amplifier 24. From the output of a two-threshold comparator 27, the sampled and regenerated binary signal goes to the output of block 6 and simultaneously to the non and the receiving input of a differential amplifier 24, at the output of which an error signal is generated,

0

five

The error signal is generated according to: with the expression

with K (and,),

where K is the gain of the differential amplifier 24;

Uj, and and are the voltages at the output and input of the two-threshold comparator 27, respectively, i.e. the error signal takes a single value if the instantaneous value of the voltage at the input of the two-threshold comparator 27 is between its

t threshold srabatshani U

pore

and and

pore

Claims (1)

Invention Formula A receiver of digital high-speed phase-shift keyed signals containing series-connected radio signal adder, phase demodulator, adder and decision and error determination unit, the first output of which is the information output of the receiver and is connected to the signal input of the adaptive transverse feedback filter that controls the input of which is connected to the second output of the decision and error detection unit and to the input of the control unit, and the diversity channel, each of which consists of The sequence controlled amplifier connected to yn ravl yuvdemu input of which is connected a corresponding output of automatic gain control unit, and an adaptive transversal filter whose output is connected to sootvetst- R blockblock 6 radio signal adder, while the output of the control unit is connected to the control inputs of the adaptive transversal filters of the diversity channels, the signal inputs of which are connected to the inputs of the automatic gain control unit, and the synchronization unit, which is connected to the decision and determination unit errors, wherein the signal inputs of the adjustable amplifiers are information inputs of the processor, characterized in that, in order to increase the noise immunity, serially connected a control signal generating unit and an adjustable feedback amplifier, the signal input and output of which are connected respectively to the output of the adaptive transverse feedback filter and the second input of the adder, the output of which is connected to the input of the control signal generating unit. FIG. 2 0U9.3