SU1487036A1 - Control system microprogram module - Google Patents

Description

The invention relates to computing and can be used to build microprogram control devices of homogeneous microprocessor systems built on the same type of modules. The purpose of the invention is to reduce the capacity of the microinstructions memory block. The microprogram module contains the microinstruction memory block, the microoperations register, the register return addresses, address multiplexer, logic conditions multiplexer, control transfer demultiplexer, return trigger, start trigger, block element OR, group of elements OR, first, second and third elements OR, first to sixth elements AND, one-shot, first and second elements of delay ”The new elements in the microprogram module, thanks to which the goal is reached, are the first to third elements OR, block OR elements, a group of OR elements, from fourth to sixth delay elements and a one-shot. V. Module implements the possibility of multiple calls to the most frequently used subroutines without losing control of the calling module.

6 Il.

The invention relates to computing and can be used to build microprogram control devices of homogeneous microprocessor computing systems built on the same type of modules.

The aim of the invention is to reduce the capacity of the memory of microinstructions "

Figures 1 and 2 show the functional diagram of the firmware of the module; on fig.Z - block diagram of the inclusion of modules; Fig "4 is a block diagram of the transfer of control between modules

no refund (a) and refund (b); figure 5 - formats of microinstructions; Fig "6 is a block diagram of the algorithm of the module.

The module contains (Fig. 1, 2) block 1 of microinstructions memory with outputs: fields 1 "1 - microoperations (return addresses), fields 1.2 - logical conditions (IDC numbers), fields 1" 3 - addresses of the next command (control transfer addresses ), 1.4 and 1 "5 - the first and second digits of the signs to identify the values of outputs 1.1. 1.2 1.3 - register 2 microcommand addresses.

1487636 A1

1487036

register 3 micro-operations, register 4 return addresses, multiplexer 5 addresses, multiplexer 6 logical conditions, demultiplexer 7 transmission up- $ pressure, return trigger 8, trigger 9 start; block of 10 elements OR; group 11.1 ... 11.η elements OR, first 12, second 13 and third 14 elements OR, third 15, first 16, neck 17, fourth 18, fifth 19 and second 20 elements AND, one-shot 21, first 22 and second 23 delay elements, inputs 24 "1..о24" η of the module control reception, the first 25.1 and second, 5 rotary 25.2 module synchronization inputs, respectively, the module stop input 26, the output 27 of the micro-operation module containing end 27.1 discharge

module operation, outputs 28.1 ... 28.η using the use of forced adressing control to other modules, bits-signs 29.1 ... 29.η of the end of the subroutine received by the calling module, bits 30.1 ... 30.η of the group of control transmission outputs of the module, the low-order bit 31 of the address of the next microcommand, which takes into account the logical conditions when the current micro-op is performed, the input 32 logic conditions of the module, the discharge 33 of the end of the subroutine.

On fig.Z - 5 the following notation is used:

KOP - opcode;

- logical conditions;

- stop;

- micro-operation;

LU

st

MO

mpm

F1,

teams

- microprogram module; F2, F2, FZ - formats of micro-natural sampling, transfer of control without return, transfer of control with return, termination of the subroutine, respectively;

Asd ~ address of the next microcommand;

“-1, * 2 - digits of the modification of the microcommand fields;

Apu - address transfer control;

№ ΜΙΙΜ - firmware number

module;

Avz - return address;

PPC - the end of the subroutine. Multiplexer 5 address serves

for choosing the direction of reception of the micro-operation code, which is the code of the adres of the first microcommand of the microprogram called · Of the eight code combinations provided by the three-digit address input A1, A2, AZ of the multiplexer, three were used,

thirty

35

40

45

50

55

The latter permit the receipt of the micro-command address code from the return address register, from other modules, · from the address part of the micro-commands in accordance with Table ₀

Address entry mx Direction of Ema in MX one 2 3 0 one one D1 one one one D 2 0 0 one dz.

The module operates in three main modes: firmware execution

sations; transfer of control to other firmware modules; transfer of control with subsequent return of control to the transmitting module.

In the initial state, the microinstructions memory block contains microinstructions codes, the memory elements are in the zero state. When a command code arrives at one of the information inputs 24.1 ... 24ot η at the output of the second element OR 13, a signal appears that triggers the module, setting the trigger trigger to one state, and opens the address multiplexer information input together with the signal from the direct trigger trigger output. The command code for the sync pulse from input 25 „1 is written to register 2 addresses and, being the address of the first microcommand of the microprogram, selects the code of this microcommand from the memory block.

In the forced addressing mode at the output of the memory block is a F1 micro-command (see Fig. 5), which by bits * 1 and * 2 enables the register of micro-operations 3 and the multiplexer 6 logical conditions, while the address code of the next micro-command goes to the logical conditions 6 input Ώ ₃ address multiplexer, which is opened by the control signal from the start trigger output. The removal of the signal from the output of the element 13 at this moment occurs due to the termination of the supply of the command code to the module input. The sync signal from input 25.2 is the code of micro-operations, and according to the following sync signal 1487036

On the input 25.1, the junction address is entered into register 2 and is fed to the address input of the memory block, the cycle repeats. In this case, the low order code of the transition address code in microinstructions of an unconditional transition, passing through the multiplexer 6 logical conditions, does not change, which is ensured by the zero code of the logical conditions number applied to the multiplexer address input. In the microcommands of the conditional transition, the code of the logical conditions number indicates the condition being checked, and depending on its performance in the operational unit at the output of multiplexer 6 appears "0" or "1",

Thus, if the condition is met, the transition address does not change (remains even), and if it fails, the address is increased by one in the low order,

In the transfer control mode, at the output of memory block 1, the F2 microinstruction appears, which by bits -ί 1 and * 2 includes the register of 3 micro-operations and the control transfer demultiplexer. The code of the number of the receiving module (output 1.2 of the memory block) goes to the address input of the demultiplexer 7 and selects one of the transmission directions 28.1 _0. , 28.n, which is used to transmit the address of the first microcommand of the subroutine from output 1.3 of the memory block.

This address through the block of 10 elements OR is fed to the input ϋ 1 of the address multiplexer. In turn, the address code, passing through the second element OR 13, generates a signal that triggers this module, setting the start trigger 9 to one state, and together with the signal from the direct trigger trigger output opens the address multiplexer input вход 1. As a result, the address code of the micro-command is sent to the address register, then it is written to the given register by the clock signal from input 25.1, and block 1 of the micro-instructions memory is accessed. Next, the algorithm of the module that takes control matches the described algorithm of forced addressing.

The transfer control mode with a return differs from the mode described above in that simultaneously with the transfer of control to another module 10

15

20

thirty

35

A fixation of the address of the next microcommand proceeds and preparation of the "Return" control signal to receive this address at the input ϋ 2 of the multiplexer 5 address. This is provided by the F 2 ⁺ microinstruction, in which the return address is written in field 1.1, and the discharge * 1 turns on the control transfer demultiplexer 7, and the label * 2 converts the return trigger 8 through the third element 15 to the one state,

In addition, the discharge * 1 on the clock signal from input 25.2 turns off this module, translating through the fourth element AND 18 and the third element OR 14, the start trigger to the zero state, as well as the signal from the output of the first 22 delay lines, resets the registers 2 to the zero state addresses and 3 microoperations.

After the subprogram is executed, at the output of block 1 of memory _and micro-operations, micro-command F 3 of the control gate is fixed, field B 1.1 of the micro-operation code, which is the last in the sub-program, contains in the low-order sign 33 of the end of the sub-program of the checkpoint, which through the second line 23 of the delay and the group of elements OR arrives at all associated with this module, which ensures that the subroutine of all modules is repeatedly accessed without loss of control.

The transmission signal causes the launch of all modules, setting the trigger 9 of the second element OR 13 into one state, and opens the inputs мульти 1 multiplexers of all modules,

40 besides the module waiting for the return, which opens the second front element AND 17 through input ϋ 2 of the address multiplexer 5 and receives the address from register 4 of input 25.1 45 from the register 4 to return to register 2 of the address.

50

55

After the subprogram is executed on the KPP signal, the return address enters through multiplexer 5 only in the module in which the trigger 8, which initiated the request to execute the subprogram, was set to one. In other modules, although the trigger 9 can be triggered by an OR 13 signal, a malfunction does not occur, since multiplexer 5 is closed and register 2 is constantly occurring

'1487036

eight

A reference is made to the zero cell of the memory block containing the zero code.

Claims (1)

Claims $ The firmware of the control system containing the microinstructions memory, address register, micro-operation register, address multiplexer, logical conditions multiplexer, trigger trigger, LC return trigger, from the first to the third elements And, the first synchronization input of the module connected to the first input of the second ele - 15 And, the output of which is connected to the first input of the first element And and to the synchronization input of the address register, the output of which is connected to the address input of the microcommand memory block, output 20 of the field of microoperations of which Connected with the information input of the register of microoperations, the output of which is the output of the microoperations of the module, the input of the logical conditions of the module is connected to the high bits of the information input of the multiplexer logical conditions, the output, the fields of the logical conditions of the microinstruction memory block 30 are connected to the control input of the multiplexer 30 logical conditions whose output connected to the low-order bit of the first information input of the address multiplexer, the output of which is connected to the information input of the address register, 35 low-order bits and the high-order bits of the output of the address field of the next microcommand of the micro-instruction memory block are connected respectively to the low-order bit of the information input of the multiplexed logical conditions and to the high-order bits of the first information input of the address multiplexer, the output of the third element I is connected to the unit setup input. LK-flip-flop trigger, the output of the first element I is connected to the synchronization input'i to the K-input of LK-flip-flop of return, the output of the trigger trigger is connected to the second input of the second element I and to the first control input of the address multiplexer, reduce the capacity of the memory block, it contains the first to the third element OR, the block of elements OR, the group of elements OR, the fourth to sixth elements AND, the return register, the demultiplexer, the first and second delay elements, the one-shot, the first digit of the local output field systematic way microinstruction storage unit .The inputs coupled to permit operation of the multiplexer and demultiplexer logical conditions and to a first input of the fourth elements. the AND element, the output of which is connected to the first input of the third OR element and the one-shot start input, the output of which is connected to the input of the first delay element, the output of which is connected to the input of setting the address register and the micro-operation register to zero, the output of the "end of operation" sign with the second input of the third OR element, the output of which is connected to the installation input to zero of the start trigger, the output of which is connected to the first input of the fifth element And, the output of which is connected to the second input of the fourth element And, the first m input of the third element And, the synchronization input of the register of micro-operations and the return register, the output of which is connected to the second information input of the address multiplexer, the second digit of the field control output of the microcommand memory block is connected to the second input of the third element And, to the resolution input of writing the return register and register micro-operations, outputs of the fields of micro-operations, logical conditions and addresses of the next micro-command are connected respectively with the information input of the return register, the address input of the demultiple litter and with the information input of the demultiplexer, the high-order bits of the first to nth outputs of which (where η is the number of control transmission directions of the module) are connected to the high-order digits, respectively, from the first to the nth control transfer outputs of the module, the output sign of the end of the program of the memory block microinstructions connected to the input of the second delay element, the output of which is connected to the first inputs of the elements of the OR group, the lower digits from the first to the nth outputs of the demul-. the typelexer is connected to the second inputs of the first through fifth elements of the OR group, the outputs of which are connected to the low-order digits of the first through fifth transmission outputs of the control module, the second synchronization input of the module is connected to the second input of the fifth element, And, 1487036 the module stop input is connected to the ~ third input of the third element OR; the first to the ηth inputs of the module control reception are connected respectively from the first to the ηth with the inputs of the block of OR elements, the output of which is connected to the third information input of the address multiplexer and from the first to the fifth inputs of the second OR element, whose output is connected to the second control the address of the multiplexer address and the input of the installation in the "1" trt start-up “In addition, the lower digits of the inputs of the module control reception are connected to the inputs of the first OR element, the output of which is connected to (n + + 1) th input of the second element OR, the second input of the first element AND, the first input of the sixth element AND, the output of which is connected to the third control input of the address multiplexer, the output of the LC return trigger is connected to the second input of the sixth element I. .one 1487036 1487036 KOP MO Fig.Z 1487036 * ί # 2 f f Ac # LU MO Fg ' one f A p y MLM MO one one Ap. at MPM A 33 ’ ABOUT <RP / f F f KPP MO | FIG. five