SU1476462A1 - Sine and cosine function pipeline computer - Google Patents

Abstract

The invention relates to computing and can be applied in specialized processors. The aim of the invention is to improve the accuracy of the calculation by introducing high-speed argument correction tools. The device contains N iterative nodes 1.1 ... 1.N (N is the width of the arguments), N correction nodes 2.1 ..... 2.N, coefficient memory block 3, first clock input 4, second clock input 5, input 6 logical zero, input 7 of the first argument, input 8 of the second argument, input 9 of the angle. The iteration nodes are computed according to the Wolder algorithm. In the correction node, the vector coordinates are corrected; this is necessary due to the deformation of the vector when it is rotated. 1 hp f-ly, 1 ill.

Description

1476462

the first argument, the input 8 of the second In the correction node, a correction argument is made, the input is 9 angles, B iteration of the vector coordinates, the necessary nodes are calculated due to the deformation of the vector when it is in accordance with the Walder algorithm. collar ,, 1 z.p. f-ly, 1 ill.

one

The invention relates to computing and can be applied in specialized processors.

The aim of the invention is to improve the accuracy of the calculation by introducing high-speed argument correction tools.

The drawing shows the functional diagram of the proposed device.

The device contains n iterative nodes 1.1,.,., 1. n (n is the length of the arguments), n-nodes correction 2.,. "., 2, n, block 3 of the coefficient memory, first clock input 4, second clock input 5, input 6 logical zero, input 7 of the first arguments; input 8 of the second argument, input 9 of the angle.

Each iteration node contains, for example, the first and second registers 10 and 11, the first and second adders-subtractors 12 and 13, the first and second shifters 14 and 15.

Corrections containing the second registers 16 and 17, the first and second subtractors 18 and 19. the first and second

If

swarm shifters 20 and 2J, comparison circuit 22, first and second switches 23 and 24,

Each knot ate first and

The device works as follows.

The calculations are carried out in accordance with the Walder algorithm. The input values of the initial vector after (i-1) iteration steps are received at the input of the 1st iteration node. With the arrival of the signal at the first clock input 4, these values are written to the first and second registers 10 and 11, respectively. The i-ro iteration node, the first and second shifters 14 and 15 of the 1st iteration node, shift the value of the arguments by i bits to the right. New values of vector coordinates received at the outputs of the first and second summers subtractors 12 and 13 of the 1st iteration node go to the 1st correction node. On the signal at the second clock input of the device, new coordinate values are written to the first and second registers 16 and 17 of the 1st correction node. The first and second switches 20 and 21 of the 1st correction node shift information by i bits to the right. The results arrive at the first inputs of the first and second switches 23 and 24 of the 1st correction node. The second inputs of these switches receive a logical zero signal. The operation of the switches 23 and 24 is performed by the comparison circuit 22, depending on co

i

coordinate relation

The results from the outputs of the first and second registers 16 and 17 of the 1st correction node and from the outputs of the first and second switches 23 and 24 are prompted to the inputs of the first and second subtractors 18 and 19 of this node. At the output of these subtractors, the corrected values of the coordinates are obtained, which are fed to the information inputs of the next (1 + 1) -th iteration node,.

The operation of the adders-readers 16 and 17 is controlled by the bit values of the iteration coefficients coming from the output of memory block 3

Claims (2)

Invention Formula 1, a conveyor device for calculating a sine and cosine function, containing n-iteration nodes (n is the width of the argument) and a memory block, coefficients, the input of the angle of the device is connected to the address input of the coefficient memory, the i-th output of which is connected to the control input iteration of the 1st iteration node, the first clock input of the device is connected to the same input of each iteration node, characterized in that, in order to improve accuracy, n-correction nodes are entered into it, with the first and second information outputs j-ro iterative node (, ..., p-1) are connected respectively to the first and second information inputs (j + l) -ro of the iteration node, the second clock input of the device is connected to the clock input of all correction nodes, the input of the logical zero of the device is connected to the same input of all correction nodes, the first and second information inputs of the first iteration node are connected with the inputs of the first and second arguments of the device, the first and second outputs of the nth correction node are connected to the first and second outputs of the device, respectively. 2. A device according to claim 1, characterized in that, in order to increase speed, each correction node contains two registers, two shifters, two switches, two subtractors and a comparison circuit, the first and second information inputs of the correction node are connected to the information inputs of the first and second registers, respectively, the clock inputs of the first and second registers are connected to the clock input of the correction node, the output of the first register is connected to the input of the reduced the first subtractor and the information input of the first shifter; the output of the second register is connected to the input of the decremented second subtractor and the information input of the second shift , the outputs of the first and second shifters are connected to the first information inputs of the first and second switches, respectively, the second information inputs of which are connected to the inputs of the logical zero of the correction node, the outputs of the first and second switches are connected to the input of the first and second subtractors, respectively, of the first and second readings switches are connected respectively to the first and second outputs of the comparison circuit, the inputs of the first and second operands of which are connected to the outputs, respectively ervogo and second registers, the outputs of the first and second subtracters, connected to the first and second information correction unit outputs.