SU1467542A1 - Pulsed d.c. voltage stabilizer - Google Patents

Abstract

The invention relates to the secondary power supply sources of electronic equipment. The aim of the invention is to increase the efficiency while maintaining dynamic stability in transient conditions. The pulse-width modulator 11, by the signal of summing amplifier 8, changes the relative duration of the on-state of the control resistor 1 so that the output to

Description

The invention relates to electrical engineering and can be used in secondary sources of electrical power for electronic equipment.

The purpose of the invention is to increase the efficiency while maintaining dynamic stability in all transient conditions.

Fig. 1 is a schematic of a DC voltage regulator; Fig. 2 shows the characteristics of the first, second and third relay elements; Fig. 3 shows timing diagrams explaining the principle of operation of a pulse voltage regulator;

The DC switching voltage regulator (FIG. 1) contains a series-connected regulating transistor 1 and an LCD filter 2 consisting of a closing diode 3, a choke 4 and a capacitor 5, the first additional transistor 6 connected through a diode 7 parallel to the choke 4 of the bcB filter 2, the summing voltage amplifier 8, the inverting input of which is connected to the output terminal for connecting the load, and the source 9 of the reference signal, the first relay element 10, the input connected to the output of the sum connected to the non-inverting input voltage amplifier 8, a pulse-pulse modulator 11 consisting of a generator of 12 clock pulses, the output of which is connected to the first input of the fourth logic

five

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five

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element 13 and the input of the former 14 sawtooth voltage, the output of which is connected to the inverting input of the comparator 15, the non-inverting input of which is connected to the output of the summing voltage amplifier 8, and the output connected to the second input of the fourth logic element and 13, a trigger 16, the input R. Of the setup. Which is connected via the second logic element NOT 17 is connected to the output of the comparator 15, the input S of the installation unit is connected to the output of the fourth logic element AND 13, and the output Q is the output of the pulse width modul a 11, the summing current amplifier 18, the inverting input of which is connected to the output of current sensor 19 connected to the load circuit, non-inverting input is connected to the output of current sensor 20 connected to the throttle 4 of the LCD filter 2, the output through diode 21 is connected to the input the second relay element 22, and through the diode 23 - to the input of the third relay element 24, the logical element OR 25, the first input of which through the first logical element HE 26 is connected to the output of the second D: 1 main element 22, the second input is connected to the output of the first relay element 20 , but Exit - to the second input of the first AND gate 27 having a first input connected to the output of flip-flop 16, and an output coupled to the control

31

the input of the regulating transistor 1, the logical element OR NOT 28, the first input of which is connected to the output of the trigger 16, the second input is connected to the output of the first relay element 10, and the output is connected to the second input of the second logic element 29, the first input of which is connected to the output of the second relay element 22, and the output to the control input of the first auxiliary transistor 6, the third logic element AND 30, the first input of which is connected to the output of the third relay element 24, the second input is connected to the output of the trigger 16, the output is connected to the control input of the second auxiliary transistor 31, connected in series with the resistor 32 between the input and output of the stabilizer.

Characteristics of the first, second and third relay elements

put in figure 2, where i IL i, f, -UH. Dead band "G; The relay elements 22 and 24 are selected depending on the amplitudes; the current pulsations of the capacitance in the steady state tf (+ + 2) i Y (. The width of the loop of the hydrograph of the relay element 10 is chosen equal to the amplitude of the linear sweep.

The principle of operation of the stabilizer is explained in the timing diagrams shown in FIG.

When the power is turned on at time t t, the output voltage, the stabilizer, the throttle current and the load current are zero. Until the time t t ,, in which the voltage. at the output of the stabilizer reaches the level of the reference voltage, at the output of the first relay element 10, whose characteristic is shown in figure 2, a high logic level, the output of the logic element OR 25 is also a high logic level, therefore, pulses exceeded by the pulse width modulus the torus 11 passes through the first logical element AND 27 to the control input of the regulating transistor 1. As long as the deviation of the output voltage from the reference voltage is greater than the amplitude

sawtooth voltage, at the time of the pulse-width modulator 11, the logic level is kept high, at which the regulating

,,

transistor 1 is open and saturated.

In the time interval to-t, or the blast of the logic element LII-NE 26, the logic level is low, the output of the second logic element I 29 is also low logic level, therefore, the first additional transistor 6 is closed. The diode 7 excludes the supply of reverse voltage to the transistor 6 in the time intervals corresponding to the open state of transistor 1. In the considered time interval s - t, the capacitor 5 of the LCD filter 2 is charged. At the same time, for currents the relation

1 1 ic + IH,

Q 5 20

35

 25 ZO. 45

55

; where IL, (- n currents through the chokesel 4, the capacitor 5 and the load, respectively. There is a condition 1c 5 i at which the output potential of the summing current amplifier 18 is a positive potential, therefore, as can be seen from the characteristics shown in figure 2 , at the output of the second relay element 22 is a high logic level, and at the output of the third relay element 24 is a low logic level, at the output of the third logic element I 30 is also a low logic level at which the second auxiliary transistor 31 is closed.

At time t t, when the deviation of the output voltage from the reference voltage is zero, a low logic level is set at the output of the first relay element 10. The condition i c i n continues to execute, therefore, the output of the second relay element 22 is high logic level, it means that the logic level at both inputs of the logic element OR 25 is low, its output level is low logic level, the control transient skinny transistor 1 is closed . At a low logic level, the output of the first relay element 10 and a high logic level at the output., The second relay element 22, are imparted by the pulse-width modulator 11, inverted by the logic circuit OR-28 and passed through the second logic circuit 29 on the control terminal entrance of the first additional tran-htor 6.

1467542

In the time interval t + t;

on which

The rush current 4 is larger than the load current, the voltage is stabilized by switching the first additional transistor 6 °. At time intervals when transistor 6 is closed, the current throttling 4 flows through the load and undergoes a backwash of the capacitor 5, while the throttle current decreases, the output voltage of the stabilizer increases.

In the time intervals when the transistor 6 is open and saturated, a current with small losses circulates in the circuit formed by the other. 4, the transistor 6 and the diode 7. By the time tt the current of the throttles 4 decreases to the value of the load current: approximately equal io i, therefore, at the outputs of the second and third relay elements .22 and 24 a low logic level, at the outputs of the second and third logic elements And 29 and 30 also a low logic level, the first and second additional transistors 6 and 31 are closed. When the logic level is low, the output of the second relay element 22 at the output of the logic element OR 25 sets a high logic level at which the pulses produced by the pshrotno-pulse modulator 11 pass through the first logic element 27 to the control input. control transistor 1; From the time t t, the stabilizer enters a steady state in which voltage is stabilized by switching the control transistor 1,

With an abrupt decrease in the load current, the process of stabilizing the voltage on the load took place in the same way as when the power was turned on. In this case, until the time t t the stabilizer was in steady state, the load current is shown in the time diagrams with a dashed line.

At time t tj, an abrupt increase in the load current occurs, the current in the choke 4 of the LCD filter 2 cannot change abruptly, so the capacitor 5 of the LCD filter 2 begins to discharge, the output voltage of the stabilizer decreases. However from the moment of time

6

t t J condition i (, i is satisfied), at which, as can be seen from the characteristics shown in FIG. 2, a low logic level is established at the output of the second relay element 22, and a high logic level at the output of the third relay element 24. Investigator0

OR 25 high logic level at which the pulses produced by the pulse-width modulator 11 pass through the first logical

5 AND 27 element to the control of the input of the regulating transistor 1. At the output of the second logic element AND 29 there is a low logic level at which the first auxiliary transistor 6 is closed, through the third logic element AND 30 and to the control input of the second additional transistor 31 produced by the pulse-width modulus of the module 11,

In the interval t- + t, when the current of the droplets 4 is less than the load current, the voltage on the load is stabilized by the in-phase switching of transistors 1 and 31. At time intervals when transistors 1 and 31 are open and full, the capacitor is charged 5 through a resistor 32 and energy storage.

in choke 4, voltage on load

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increases, the current drops 4 increases. At time intervals when transistors 1 and 31 are closed, capacitor 5 is discharged to the load, the current

The throttle 4 decreases, the output voltage of the stabilizer decreases. By the time t t 4 current throttle 4 reaches the current value. load, approximately fulfilled et45

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with condition 1 1,

A transition to the established mode.

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the invention

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A DC voltage regulator containing a regulating transistor connected between the input terminal and the first output of the first current sensor connected in series and the filter Drossel, a closing diode connected between the common point of the regulating transistor and the series connected

71

The first current AarqviKOM and the filter choke and the common bus, the filter capacitor connected in series with the second current sensor between the output output and the common bus, the voltage mismatch amplifier, one input connected to the output output, and the other input connected to the reference voltage source, pulse-width modulator, one input connected to the output of the error amplifier for voltage, and another input connected to the output of the sawtooth generator, the first optional transistor connected in series with a resistor between the input terminal and the common point of the filter capacitor with the second current sensor and the input connected via the first logic element to the output of the pulse-width modulator, the second auxiliary transistor connected in parallel with the series-connected filter choke to the first current sensor , the current error amplifier connected by inputs to the outputs of the first and second current sensors, the first and second relay elements connected to the output of the error amplifier by. current, the second and third logical elements are AND, the logical element is NOT and the third relay element, the input of the second logical element AND is connected to the control input of the second additional transistor, the output of the third logical element AND from

eight

one with the control input of the porynvr transistor, the first input of the third element I is connected to the output of a pulse-width modulator, characterized in that, in order to increase efficiency while maintaining dynamic stability in all transient modes, a logical element OR-NOT is introduced into it , the logical element OR, and the third relay element is made with a hysteresis characteristic, and the output of the error amplifier is connected to the input of the third relay element, the output of which is connected to the first input of the logical the element OR NOT and the first input of the logical element OR, the output of the first relay element is connected to the first input of the first logical element AND, the output of the second relay element is connected to the first input of the second logical element AND and through the logical element is NOT connected to the second input of the logical element OR output which is connected to the second input of the third logical element AND, the output of the pulse-width modulator is connected to the second input of the logical element OR NOT, the output of the logical element OR NOT connected to watts rum input of the second AND gate, the total point of series connected filter capacitor with the second current sensor .Connect to the second terminal of series-connected filter choke and the first current sensor.

Claims (1)

Claim A pulsed DC voltage regulator comprising a control transistor connected between the input terminal and the first terminal of the first 55 current sensor and the filter choke, a diode connected between the common point of the control transistor and the first sensor connected in series with the filter choke and a common bus, a capacitor a filter connected in series with a second current sensor between the output terminal and the common bus, voltage imbalance amplifier, one input per connected to the output terminal, and connected to the reference voltage source by another input, a pulse-width modulator, connected to the OUTPUT of the voltage mismatch amplifier by one input, and connected to the output of a sawtooth voltage generator by the other input, the first additional transistor connected in series with a resistor between the input output and a common point of the filter capacitor with a second current sensor and an input connected through the first logic element to the output of the pulse-width modulator, the second an additional transistor connected in parallel with the filter choke connected to the first current sensor in series, a current mismatch amplifier connected to the outputs of the first and second current sensors, the first and second relay elements connected to the output of the current mismatch amplifier, second and third logical elements And, the logical element is NOT and the third relay element, and the input of the second logical element AND is connected to the control input of the second additional transistor, the output of the third logical ele And is connected to the control input of the regulating transistor, the first input of the third AND element is connected to the output of a pulse-width modulator, characterized in that, in order to increase the efficiency while maintaining dynamic stability in all transient modes, an IQ logic element OR-HE is introduced into it , OR logic element, and the third relay element is made with a hysteresis characteristic, and the output of the voltage mismatch amplifier 15 is connected to the input of the third relay element, the output of which is connected to the first input logic gate OR-HE and the first input of logic gate OR, the output of the first 2Q relay element is connected to the first input of the first logic gate AND, the output of the second relay element is connected to the first input of the second logic gate AND 25 logic element is NOT connected to the second input of the logic gate OR whose output is connected to the second input of the third logical element AND, the output of the pulse-width 3θth modulator is connected to the second input of the logical element OR-NOT, the output of the logical element OR-NOT connected to the second input of the second logic element AND, the common point of the series-connected filter capacitor35 with the second current sensor. connected to the second output of the series-connected filter choke and the first current sensor. Ufoxii Ji / t Ufuxto Fi ", g Fig.Z